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Description
  • Advanced image processing algorithms usually require high computing performance. Today's personal computers (PCs) offer satisfying resources for implementation of image processing tasks. However, as the image processing techniques are becoming more and more complex other implementation possibilities have to be searched. Since image processing algorithms usually comply with the Single Instruction Multiple Data (SIMD) model, implementation efforts using such hardware resources are suitable. An example of the SIMD hardware component available nowadays is the graphics processor (GPU) embedded in modern graphics cards manufactured for PCs. In this paper, the implementation of a blind image deconvolution algorithm using graphics processor as the SIMD computing resource is presented. The resulting performance is compared to the performance achieved on a common general-purpose processor (CPU).
  • Advanced image processing algorithms usually require high computing performance. Today's personal computers (PCs) offer satisfying resources for implementation of image processing tasks. However, as the image processing techniques are becoming more and more complex other implementation possibilities have to be searched. Since image processing algorithms usually comply with the Single Instruction Multiple Data (SIMD) model, implementation efforts using such hardware resources are suitable. An example of the SIMD hardware component available nowadays is the graphics processor (GPU) embedded in modern graphics cards manufactured for PCs. In this paper, the implementation of a blind image deconvolution algorithm using graphics processor as the SIMD computing resource is presented. The resulting performance is compared to the performance achieved on a common general-purpose processor (CPU). (en)
Title
  • Blind image deconvolution algorithm on NVIDIA CUDA platform
  • Blind image deconvolution algorithm on NVIDIA CUDA platform (en)
skos:prefLabel
  • Blind image deconvolution algorithm on NVIDIA CUDA platform
  • Blind image deconvolution algorithm on NVIDIA CUDA platform (en)
skos:notation
  • RIV/67985556:_____/10:00342300!RIV11-MSM-67985556
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(7H09005), Z(AV0Z10750506)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 249052
http://linked.open...ai/riv/idVysledku
  • RIV/67985556:_____/10:00342300
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • convolution; CUDA; SIMD; HW implementation (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [F03FF854B0BC]
http://linked.open...v/mistoKonaniAkce
  • Vienna
http://linked.open...i/riv/mistoVydani
  • Vienna
http://linked.open...i/riv/nazevZdroje
  • Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Kamenický, Jan
  • Heřmánek, Antonín
  • Mazanec, Tomáš
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • Institute of Electrical and Electronics Engineers
https://schema.org/isbn
  • 978-1-4244-6610-8
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