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Description
  • Traditional design techniques for FPGAs are based on using hardware description languages, with functional and postplace-and-route simulation as a means to check design correctness and remove detected errors. With large complexity of things to be designed it is necessary to introduce new design approaches that will increase the level of abstraction while maintaining the necessary efficiency of a computation performed in hardware that we are used to today. This paper presents one such methodology that builds upon existing research in multithreading, object composability and encapsulation, partial runtime reconfiguration, and self adaptation. The methodology is based on currently available FPGA design tools. The efficiency of the methodology is evaluated on basic vector and matrix operations.
  • Traditional design techniques for FPGAs are based on using hardware description languages, with functional and postplace-and-route simulation as a means to check design correctness and remove detected errors. With large complexity of things to be designed it is necessary to introduce new design approaches that will increase the level of abstraction while maintaining the necessary efficiency of a computation performed in hardware that we are used to today. This paper presents one such methodology that builds upon existing research in multithreading, object composability and encapsulation, partial runtime reconfiguration, and self adaptation. The methodology is based on currently available FPGA design tools. The efficiency of the methodology is evaluated on basic vector and matrix operations. (en)
  • Tradiční návrhové techniky pro FPGA obvody jsou založené na jazycích popisujících daný hardware a na funkcionální a postplace-and-route simulaci. Tedy na ověřování správnosti návrhu, detekci chyb a jejich následném odstranění. S rostoucí složitostí navrhovaných systémů je vhodné si uvést takové návrhové přístupy, které zvyšují úroveň abstrakce a zároveň zachovávají efektivitu navrohovaného hardwaru. Tento článek jednu takovou návrhovou metodu představuje. Je založena na výzkumu zabývajícím se více vláknovými výpočty, zapouzdřením a skládatelnosti objektů, částečné dynamické rekonfiguraci a samo adaptaci. Metodologie je založena na, v současné době, dostupných nástrojích pro návrhy v FPGA obvodech. Efektivita, touto metodou navrženého hardwaru, je doložena pomocí základních vektorových a maticových operací. (cs)
Title
  • Increasing the Level of Abstraction in FPGA-based Designes
  • Zvyšování úrovně abstrakce v návrzích založených na FPGA (cs)
  • Increasing the Level of Abstraction in FPGA-based Designes (en)
skos:prefLabel
  • Increasing the Level of Abstraction in FPGA-based Designes
  • Zvyšování úrovně abstrakce v návrzích založených na FPGA (cs)
  • Increasing the Level of Abstraction in FPGA-based Designes (en)
skos:notation
  • RIV/67985556:_____/08:00313274!RIV09-AV0-67985556
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • Z(AV0Z10750506)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 371852
http://linked.open...ai/riv/idVysledku
  • RIV/67985556:_____/08:00313274
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • FPGA; dataflow; floating-point (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [28638DC43319]
http://linked.open...v/mistoKonaniAkce
  • Heidelberg
http://linked.open...i/riv/mistoVydani
  • Heidelberg
http://linked.open...i/riv/nazevZdroje
  • International Conference on Field Programmable Logic and Applications
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Daněk, Martin
  • Kadlec, Jiří
  • Kohout, Lukáš
  • Bartosinski, Roman
http://linked.open...vavai/riv/typAkce
http://linked.open...ain/vavai/riv/wos
  • 000263578100001
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • Kirchhoff Institute for Physics
https://schema.org/isbn
  • 978-1-4244-1961-6
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