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  • The paper deals with floating-point-like implementation of the GSFAP algorithm using FPGA hardware. We present an optimized core for the GSFAP, built using logarithmic arithmetic which provides very low cost multiplication and division. The resulting GSFAP core can be clocked at more than 80 MHz on the one million gate Xilinx XC2V1000-4 device. It can be used to implement filters of orders 20 to 1000 with a sampling rate exceeding 50 kHz.
  • The paper deals with floating-point-like implementation of the GSFAP algorithm using FPGA hardware. We present an optimized core for the GSFAP, built using logarithmic arithmetic which provides very low cost multiplication and division. The resulting GSFAP core can be clocked at more than 80 MHz on the one million gate Xilinx XC2V1000-4 device. It can be used to implement filters of orders 20 to 1000 with a sampling rate exceeding 50 kHz. (en)
Title
  • FPGA Implementation of Adaptive Filters based on GSFAP using Log Arithmetic
  • FPGA Implementation of Adaptive Filters based on GSFAP using Log Arithmetic (en)
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  • FPGA Implementation of Adaptive Filters based on GSFAP using Log Arithmetic
  • FPGA Implementation of Adaptive Filters based on GSFAP using Log Arithmetic (en)
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  • RIV/67985556:_____/06:00042476!RIV10-AV0-67985556
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  • Z(AV0Z10750506)
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  • 476258
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  • RIV/67985556:_____/06:00042476
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  • adaptive filter; DSP; affine projection; logarithmic arithmetic; FPGA (en)
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  • [E7F0B593B2D4]
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  • Banff
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  • Calgary
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  • Proceedings of The 2006 IEEE Workshop on Signal Processing Systems Design and Implementation
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  • Schier, Jan
  • Tichý, Milan
  • Gregg, D.
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  • IEEE Signal Processing Society
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  • 978-1-4244-0382-0
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