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Description
  • Částečná dynamická rekonfigurace umožňuje zvyšovat funkční hustotu návrhu, což ale vede ke složitějším metodám návrhu. Tento článek popisuje metodologii a návrhový postup pro rekonfigurovatelná zapojení z oblasti zpracování signálů a řídící techniky. Popisovaný postup začíná popisem v prostředí Matlab/Simulink, který je převeden do Handel-C a pak přeložen do VHDL a EDIFu a konfigurační informace pro FPGA obvody. Postup je předveden na příkladech. (cs)
  • This paper describes a methodology and design flow for designs with dynamic reconfiguration in the DSP and control domain. The described design flow starts with a description an Matlab/Simulink that is converted to Handel-C and then compiled through VHDL to EDIF, and finally to FPGA configuration. The methodology and design flow are demonstrated on implementation examples with simple floating-point IP cores targetting the Atmel AT94K FPSLIC device.
  • This paper describes a methodology and design flow for designs with dynamic reconfiguration in the DSP and control domain. The described design flow starts with a description an Matlab/Simulink that is converted to Handel-C and then compiled through VHDL to EDIF, and finally to FPGA configuration. The methodology and design flow are demonstrated on implementation examples with simple floating-point IP cores targetting the Atmel AT94K FPSLIC device. (en)
Title
  • Design and verification methodology for reconfigurable designs in Atmel FPSLIC
  • Design and verification methodology for reconfigurable designs in Atmel FPSLIC (en)
  • Metody návrhu a verifikace pro rekonfigurovatelné návrhy v obvodu Atmel FPSLIC (cs)
skos:prefLabel
  • Design and verification methodology for reconfigurable designs in Atmel FPSLIC
  • Design and verification methodology for reconfigurable designs in Atmel FPSLIC (en)
  • Metody návrhu a verifikace pro rekonfigurovatelné návrhy v obvodu Atmel FPSLIC (cs)
skos:notation
  • RIV/67985556:_____/06:00040204!RIV07-AV0-67985556
http://linked.open.../vavai/riv/strany
  • 79;80
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GA102/04/2137), Z(AV0Z10750506)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 470914
http://linked.open...ai/riv/idVysledku
  • RIV/67985556:_____/06:00040204
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • FPGA; dynamic reconfiguration; FPSLIC; floating-point IP cores; design flow (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [61402075F797]
http://linked.open...v/mistoKonaniAkce
  • Prague
http://linked.open...i/riv/mistoVydani
  • Prague
http://linked.open...i/riv/nazevZdroje
  • Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits adn Systems
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Daněk, Martin
  • Kadlec, Jiří
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • České vysoké učení technické v Praze
https://schema.org/isbn
  • 1-4244-0184-4
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