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  • Optimization of an FPGA implementation of iterative algorithms with nested loops is treated, using Integer Linear Programming. An example of the FI-CMA blind equalization algorithm is considered, using limited (and small) number of arithmetic units with non-zero latency. The optimization is based on cyclic scheduling with precedence delays for distinct dedicated processors. An optimally scheduled abstract model is constructed, modeling imperfectly nested loops.
  • Optimization of an FPGA implementation of iterative algorithms with nested loops is treated, using Integer Linear Programming. An example of the FI-CMA blind equalization algorithm is considered, using limited (and small) number of arithmetic units with non-zero latency. The optimization is based on cyclic scheduling with precedence delays for distinct dedicated processors. An optimally scheduled abstract model is constructed, modeling imperfectly nested loops. (en)
Title
  • Optimization of finite interval CMA implementation for FPGA
  • Optimization of finite interval CMA implementation for FPGA (en)
skos:prefLabel
  • Optimization of finite interval CMA implementation for FPGA
  • Optimization of finite interval CMA implementation for FPGA (en)
skos:notation
  • RIV/67985556:_____/05:00411508!RIV10-MSM-67985556
http://linked.open...avai/riv/aktivita
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  • P(1ET300750402), P(1M0567), Z(AV0Z10750506)
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  • 534891
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  • RIV/67985556:_____/05:00411508
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  • CMA; FPGA; logarithmic arithmetic; cyclic scheduling (en)
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  • [74F894787274]
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  • Athens
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  • Athens
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  • Proceedings of the IEEE Workshop on Signal Processing Systems. SiPS 2005
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  • Schier, Jan
  • Heřmánek, Antonín
  • Šůcha, P.
  • Hanzálek, Z.
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number of pages
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  • IEEE
https://schema.org/isbn
  • 0-7803-9333-3
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