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Description
  • An FPGA implementation of the FI-CMA algorithm using the Virtex-E and Virtex-II devices is presented. The algorithm consists of two parts: one, performing batch-QR decomposition of the data matrix, and second, used for an iterative equalizer optimization, using the columns of the Q-matrix as input. The resource reuse and minimization of the total latency have been emphasized. Logarithmic arithmetic library has been used for floating point calculations, required in algorithm.
  • An FPGA implementation of the FI-CMA algorithm using the Virtex-E and Virtex-II devices is presented. The algorithm consists of two parts: one, performing batch-QR decomposition of the data matrix, and second, used for an iterative equalizer optimization, using the columns of the Q-matrix as input. The resource reuse and minimization of the total latency have been emphasized. Logarithmic arithmetic library has been used for floating point calculations, required in algorithm. (en)
Title
  • FPGA implementation of Finite Interval CMA
  • FPGA implementation of Finite Interval CMA (en)
skos:prefLabel
  • FPGA implementation of Finite Interval CMA
  • FPGA implementation of Finite Interval CMA (en)
skos:notation
  • RIV/67985556:_____/05:00411312!RIV10-AV0-67985556
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(1ET300750402), Z(AV0Z10750506)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 522033
http://linked.open...ai/riv/idVysledku
  • RIV/67985556:_____/05:00411312
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • CMA algorithm; FPGA; data matrix (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [2A619F235F7F]
http://linked.open...v/mistoKonaniAkce
  • Antverpy
http://linked.open...i/riv/mistoVydani
  • Antverpy
http://linked.open...i/riv/nazevZdroje
  • Proceedings of the first annual IEEE BENELUX/DSP Valley Signal Processing Symposium. SPS-DARTS 2005
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Schier, Jan
  • Heřmánek, Antonín
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • IEEE
https://schema.org/isbn
  • 0-7803-9333-3
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