About: AVR core supported dynamic reconfiguration

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	Tento text presentuje univerzální platformu s externí FLASH pamětí pro dynamickou rekonfiguraci na obvodu AT94K FPSLIC od firmy Atmel. Platforma vytváří transparentní infrastrukturu pro softwarově řízenou dynamickou rekonfiguraci na FPGA (cs) This paper presents a software core for an universal econfiguration system-on-a-programmable chip platform based on Atmel AT94K FPSLIC with an external FLASH memory. The AVR core controls basic functions that together with the FPSLIC platform creates a transparent infrastructure for software-driven FPGA reconfiguration. This paper presents a software core for an universal econfiguration system-on-a-programmable chip platform based on Atmel AT94K FPSLIC with an external FLASH memory. The AVR core controls basic functions that together with the FPSLIC platform creates a transparent infrastructure for software-driven FPGA reconfiguration. (en)
Title	AVR core supported dynamic reconfiguration AVR core supported dynamic reconfiguration (en) Podpora dynamické rekonfigurace pro AVR (cs)
skos:prefLabel	AVR core supported dynamic reconfiguration AVR core supported dynamic reconfiguration (en) Podpora dynamické rekonfigurace pro AVR (cs)
skos:notation	RIV/67985556:_____/04:00106383!RIV/2005/AV0/A16005/N
http://linked.open.../vavai/riv/strany	1;5
http://linked.open...avai/riv/aktivita	Z
http://linked.open...avai/riv/aktivity	Z(AV0Z1075907)
http://linked.open...vai/riv/dodaniDat	2005
http://linked.open...aciTvurceVysledku	Honzík, Petr
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Ústav teorie informace a automatizace AV ČR, v. v. i.
http://linked.open...dnocenehoVysledku	555731
http://linked.open...ai/riv/idVysledku	RIV/67985556:_____/04:00106383
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	dynamic reconfiguration;FPGA;AVR core (en)
http://linked.open.../riv/klicoveSlovo	dynamic reconfiguration FPGA AVR core
http://linked.open...ontrolniKodProRIV	[5DE7A257F2BF]
http://linked.open...v/mistoKonaniAkce	Praha
http://linked.open...i/riv/mistoVydani	Praha
http://linked.open...i/riv/nazevZdroje	POSTER 2004. Proceedings of the 8th International Student Conference on Electrical Engineering
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	1 (xsd:int)
http://linked.open...cetTvurcuVysledku	1 (xsd:int)
http://linked.open...UplatneniVysledku	2004
http://linked.open...iv/tvurceVysledku	Honzík, Petr
http://linked.open...vavai/riv/typAkce	EUR - Evropská
http://linked.open.../riv/zahajeniAkce	2004-05-20 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Uncertainty methods in theoretical cybernetics: system identification, information processing, decision-making, and control
number of pages	5 (xsd:int)
http://purl.org/ne...btex#hasPublisher	České vysoké učení technické v Praze. Fakulta elektrotechnická

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