About: Using logarithmic arithmetic to implement the Recursive Least Squares (QR) algorithm in FPGA

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About: Using logarithmic arithmetic to implement the Recursive Least Squares (QR) algorithm in FPGA Goto Sponge NotDistinct Permalink

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	In this paper, an FPGA implementation of the QR update algorithm with Givens rotations using the High Speed Logarithmic Arithmetic (HSLA) library is outlined. An advantage of this approach is low latency and accurate computation (comparable with single-precision floating point) of the operations. In this paper, an FPGA implementation of the QR update algorithm with Givens rotations using the High Speed Logarithmic Arithmetic (HSLA) library is outlined. An advantage of this approach is low latency and accurate computation (comparable with single-precision floating point) of the operations. (en) V článku je popsána FPGA implementace algoritmu pro QR aktualizaci pomocí Givensových rotací s použitím High Speed Logarithmic Arithmetic (HSLA) aritmetické knihovny. Výhodou tohoto způsobu implementace je malá latence výpočtu a dostatečná přesnost operací (srovnatelná s výpočty v plovoucí řádové čárce s jednoduchou přesností) (cs)
Title	Using logarithmic arithmetic to implement the Recursive Least Squares (QR) algorithm in FPGA Using logarithmic arithmetic to implement the Recursive Least Squares (QR) algorithm in FPGA (en) Použití logaritmické aritmetiky pro implementaci výpočtu rekurzivních nejmenších čtverců v FPGA obvodu (cs)
skos:prefLabel	Using logarithmic arithmetic to implement the Recursive Least Squares (QR) algorithm in FPGA Using logarithmic arithmetic to implement the Recursive Least Squares (QR) algorithm in FPGA (en) Použití logaritmické aritmetiky pro implementaci výpočtu rekurzivních nejmenších čtverců v FPGA obvodu (cs)
skos:notation	RIV/67985556:_____/04:00106326!RIV/2005/MSM/A16005/N
http://linked.open.../vavai/riv/strany	1149;1151
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(1ET300750402), P(1ET400750408), P(LN00B096), Z(AV0Z1075907)
http://linked.open...vai/riv/dodaniDat	2005
http://linked.open...aciTvurceVysledku	Schier, Jan Heřmánek, Antonín
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Ústav teorie informace a automatizace AV ČR, v. v. i.
http://linked.open...dnocenehoVysledku	591742
http://linked.open...ai/riv/idVysledku	RIV/67985556:_____/04:00106326
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	QR update;FPGA;logarithmic arithmetic (en)
http://linked.open.../riv/klicoveSlovo	FPGA QR update logarithmic arithmetic
http://linked.open...ontrolniKodProRIV	[4D5981CC63EB]
http://linked.open...v/mistoKonaniAkce	Antverp
http://linked.open...i/riv/mistoVydani	Berlin
http://linked.open...i/riv/nazevZdroje	Field-Programmable Logic and Applications. 14th International Conference FPL 2004. Proceedings
http://linked.open...in/vavai/riv/obor	BD
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...vavai/riv/projekt	Specification of quantitative criteria and optimalization of resources for broadband access networks Rapid prototyping tools for development of HW-accelerated embedded image- and video-processing applications Center for Applied Cybernetics
http://linked.open...UplatneniVysledku	2004
http://linked.open...iv/tvurceVysledku	Schier, Jan Heřmánek, Antonín
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2004-08-30 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Uncertainty methods in theoretical cybernetics: system identification, information processing, decision-making, and control
number of pages	3 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Springer-Verlag
https://schema.org/isbn	3-540-22989-2

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