About: Lattice for FPGAs using logarithmic arithmetic.

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	Presented here are implementations of a complete RLS Lattice cores for Virtex. Their computational parallelism and ease of pipelining lead to easy mapping on FPGA. Internally, the computations are based on 32bit or 20bit logarithmic arithmetic (LNS). Compared are the 32bit LNS-SINGLE-ALU and 20bit LNS-QUAD-ALU versions. On Virtex XCV2000E-6, these use 27%, 54% or 40% of slices respectively and run at 50, 35 and 42 MHz on the Celoxica RC1000 board. Presented here are implementations of a complete RLS Lattice cores for Virtex. Their computational parallelism and ease of pipelining lead to easy mapping on FPGA. Internally, the computations are based on 32bit or 20bit logarithmic arithmetic (LNS). Compared are the 32bit LNS-SINGLE-ALU and 20bit LNS-QUAD-ALU versions. On Virtex XCV2000E-6, these use 27%, 54% or 40% of slices respectively and run at 50, 35 and 42 MHz on the Celoxica RC1000 board. (en)
Title	Lattice for FPGAs using logarithmic arithmetic. Lattice for FPGAs using logarithmic arithmetic. (en)
skos:prefLabel	Lattice for FPGAs using logarithmic arithmetic. Lattice for FPGAs using logarithmic arithmetic. (en)
skos:notation	RIV/67985556:_____/02:16020051!RIV/2003/AV0/A16003/N
http://linked.open.../vavai/riv/strany	53;56
http://linked.open...avai/riv/aktivita	Z
http://linked.open...avai/riv/aktivity	Z(AV0Z1075907)
http://linked.open...iv/cisloPeriodika	906
http://linked.open...vai/riv/dodaniDat	2003
http://linked.open...aciTvurceVysledku	Matoušek, Rudolf Líčko, Miroslav Kadlec, Jiří Heřmánek, Antonín Tichý, Milan
http://linked.open.../riv/druhVysledku	J - Článek v odborném periodiku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Ústav teorie informace a automatizace AV ČR, v. v. i.
http://linked.open...dnocenehoVysledku	651606
http://linked.open...ai/riv/idVysledku	RIV/67985556:_____/02:16020051
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	lattice Rls algorithm; FPGA; logarithmic arithmetic (en)
http://linked.open.../riv/klicoveSlovo	FPGA lattice Rls algorithm logarithmic arithmetic
http://linked.open...odStatuVydavatele	GB - Spojené království Velké Británie a Severního Irska
http://linked.open...ontrolniKodProRIV	[F5A6789F542B]
http://linked.open...i/riv/nazevZdroje	Electronic Engineering Design
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	5 (xsd:int)
http://linked.open...cetTvurcuVysledku	5 (xsd:int)
http://linked.open...ocetUcastnikuAkce	0 (xsd:int)
http://linked.open...nichUcastnikuAkce	0 (xsd:int)
http://linked.open...UplatneniVysledku	2002
http://linked.open...v/svazekPeriodika	74
http://linked.open...iv/tvurceVysledku	Kadlec, Jiří Heřmánek, Antonín Tichý, Milan Matoušek, Rudolf Líčko, Miroslav
http://linked.open...n/vavai/riv/zamer	Uncertainty methods in theoretical cybernetics: system identification, information processing, decision-making, and control
issn	0013-4902
number of pages	4 (xsd:int)

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