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  • This paper deals with the architecture for effective merging of high-speed network streams into one communication line. Networking hardware typically has more than one Ethernet port and if we want to transfer data via single communication bus (PCI-Express, for example) we need to merge all the Ethernet lines into one wide data stream. This paper discusses various approaches of dealing with the emerging issues related to very wide data busses and their alignment. The main contribution of this paper is the introduction of the architecture for merging of high-speed network streams as effective as possible. We use Virtex-7 equipped FPGA card to implement and test our architecture.
  • This paper deals with the architecture for effective merging of high-speed network streams into one communication line. Networking hardware typically has more than one Ethernet port and if we want to transfer data via single communication bus (PCI-Express, for example) we need to merge all the Ethernet lines into one wide data stream. This paper discusses various approaches of dealing with the emerging issues related to very wide data busses and their alignment. The main contribution of this paper is the introduction of the architecture for merging of high-speed network streams as effective as possible. We use Virtex-7 equipped FPGA card to implement and test our architecture. (en)
Title
  • Architecture of Effective High-Speed Network Stream Merger
  • Architecture of Effective High-Speed Network Stream Merger (en)
skos:prefLabel
  • Architecture of Effective High-Speed Network Stream Merger
  • Architecture of Effective High-Speed Network Stream Merger (en)
skos:notation
  • RIV/63839172:_____/14:10130442!RIV15-MSM-63839172
http://linked.open...avai/riv/aktivita
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  • I, P(LM2010005), S
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
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  • 4014
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  • RIV/63839172:_____/14:10130442
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  • 40 and 100 Gbps Ethernet; Effective High-Speed Network Stream Merging; FPGA (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [15E676F70C35]
http://linked.open...v/mistoKonaniAkce
  • Verona, Itálie
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  • Verona, Itálie
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  • Proceedings of 17th Euromicro Conference on Digital System Design
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  • Kubátová, Hana
  • Puš, Viktor
  • Benáček, Pavel
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number of pages
http://bibframe.org/vocab/doi
  • 10.1109/DSD.2014.25
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  • IEEE
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  • 978-1-4799-5793-4
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