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  • The aim of this paper is a hardware realization of a statistical anomaly detection method as a part of high-speed monitoring probe for computer networks. The sequential Non-Parametric Cumulative Sum (NP-CUSUM) procedure is the detection method of our choice and we use an FPGA based accelerator card as the target platform. For rapid detection algorithm development, a high-level synthesis (HLS) approach is applied. Furthermore, we combine HLS with the usage of Software Defined Monitoring (SDM) framework on the monitoring probe, which enables easy deployment of various hardware-accelerated monitoring applications into high-speed networks. Our implementation of NP-CUSUM algorithm serves as hardware plug-in for SDM and realizes the detection of network attacks and anomalies directly in FPGA. Additionally, the parallel nature of the FPGA technology allows us to realize multiple different detections simultaneously without any losses in throughput. Our experimental results show the feasibility of HLS and SDM combination for effective realization of traffic analysis and anomaly detection in networks with speeds up to 100 Gb/s.
  • The aim of this paper is a hardware realization of a statistical anomaly detection method as a part of high-speed monitoring probe for computer networks. The sequential Non-Parametric Cumulative Sum (NP-CUSUM) procedure is the detection method of our choice and we use an FPGA based accelerator card as the target platform. For rapid detection algorithm development, a high-level synthesis (HLS) approach is applied. Furthermore, we combine HLS with the usage of Software Defined Monitoring (SDM) framework on the monitoring probe, which enables easy deployment of various hardware-accelerated monitoring applications into high-speed networks. Our implementation of NP-CUSUM algorithm serves as hardware plug-in for SDM and realizes the detection of network attacks and anomalies directly in FPGA. Additionally, the parallel nature of the FPGA technology allows us to realize multiple different detections simultaneously without any losses in throughput. Our experimental results show the feasibility of HLS and SDM combination for effective realization of traffic analysis and anomaly detection in networks with speeds up to 100 Gb/s. (en)
Title
  • FPGA Accelerated Change-Point Detection Method for 100Gb/s Networks
  • FPGA Accelerated Change-Point Detection Method for 100Gb/s Networks (en)
skos:prefLabel
  • FPGA Accelerated Change-Point Detection Method for 100Gb/s Networks
  • FPGA Accelerated Change-Point Detection Method for 100Gb/s Networks (en)
skos:notation
  • RIV/63839172:_____/14:10130397!RIV15-MSM-63839172
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(LM2010005), V
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 17379
http://linked.open...ai/riv/idVysledku
  • RIV/63839172:_____/14:10130397
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • NP-CUSUM; high-level synthesis; anomaly detection; Software Defined Monitoring; FPGA (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [A32CED3AB4D7]
http://linked.open...v/mistoKonaniAkce
  • Telč, Czech Republic
http://linked.open...i/riv/mistoVydani
  • Brno
http://linked.open...i/riv/nazevZdroje
  • MEMICS proceedings 2014
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Čejka, Tomáš
  • Kubátová, Hana
  • Benáček, Pavel
  • Kekely, Lukáš
  • Blažek, Rudolf B.
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
number of pages
http://purl.org/ne...btex#hasPublisher
  • NOVPRESS
https://schema.org/isbn
  • 978-80-214-5022-6
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