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rdf:type
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Description
| - A device based on the proposed solution allows high-definition video transmissions with low latency over an asynchronous packet computer network such as Ethernet. The transmitter and receiver comprise a video input or output module, an FPGA board, and an optical transceiver for transmission and reception of a signal over the Ethernet network. The principle of the new device is that the receiver comprises one or more tunable oscillators connected to the FPGA board comprising a module for packet reception, and one or more sets of modules for video data processing.
- A device based on the proposed solution allows high-definition video transmissions with low latency over an asynchronous packet computer network such as Ethernet. The transmitter and receiver comprise a video input or output module, an FPGA board, and an optical transceiver for transmission and reception of a signal over the Ethernet network. The principle of the new device is that the receiver comprises one or more tunable oscillators connected to the FPGA board comprising a module for packet reception, and one or more sets of modules for video data processing. (en)
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Title
| - DEVICE FOR RECEIVING OF HIGH-DEFINITION VIDEO SIGNAL WITH LOW-LATENCY TRANSMISSION OVER AN ASYNCHRONOUS PACKET NETWORK
- DEVICE FOR RECEIVING OF HIGH-DEFINITION VIDEO SIGNAL WITH LOW-LATENCY TRANSMISSION OVER AN ASYNCHRONOUS PACKET NETWORK (en)
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skos:prefLabel
| - DEVICE FOR RECEIVING OF HIGH-DEFINITION VIDEO SIGNAL WITH LOW-LATENCY TRANSMISSION OVER AN ASYNCHRONOUS PACKET NETWORK
- DEVICE FOR RECEIVING OF HIGH-DEFINITION VIDEO SIGNAL WITH LOW-LATENCY TRANSMISSION OVER AN ASYNCHRONOUS PACKET NETWORK (en)
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skos:notation
| - RIV/63839172:_____/14:10130154!RIV15-MSM-63839172
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http://linked.open...avai/riv/aktivita
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http://linked.open...avai/riv/aktivity
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http://linked.open...cisloPatentuVzoru
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http://linked.open...eleniPatentuVzoru
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http://linked.open...vai/riv/dodaniDat
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http://linked.open...aciTvurceVysledku
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http://linked.open.../riv/druhVysledku
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http://linked.open...iv/duvernostUdaju
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http://linked.open...titaPredkladatele
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http://linked.open...dnocenehoVysledku
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http://linked.open...ai/riv/idVysledku
| - RIV/63839172:_____/14:10130154
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http://linked.open...riv/jazykVysledku
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http://linked.open.../riv/klicovaSlova
| - network latency; FPGA boards; video transmission (en)
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http://linked.open.../riv/klicoveSlovo
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http://linked.open...ontrolniKodProRIV
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http://linked.open.../licencniPoplatek
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http://linked.open...ydaniPatentuVzoru
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http://linked.open...atelePatentuVzoru
| - United States Patent and Trademark Office (USPTO)
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http://linked.open...in/vavai/riv/obor
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http://linked.open...ichTvurcuVysledku
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http://linked.open...cetTvurcuVysledku
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http://linked.open...vavai/riv/projekt
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http://linked.open...UplatneniVysledku
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http://linked.open...ydaniPatentuVzoru
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http://linked.open...iv/tvurceVysledku
| - Halák, Jiří
- Ubik, Sven
- Žejdl, Petr
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http://linked.open...mniOchranaPatentu
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http://linked.open...avai/riv/vlastnik
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http://linked.open...itiJinymSubjektem
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http://linked.open...uzitiPatentuVzoru
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http://linked.open...stnikPatentuVzoru
| - CESNET, zájmové sdružení právnických osob
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