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Description
  • This technical report describes design, implementation and evaluation of a hardware-accelerated system for distribution of network traffic among processor cores. The workload associated with network packet processing is split into several parts of similar size, and each core performs the required operation only on certain part of network packets. Packets of one flow are always processed by the same core. Hardware acceleration is used to perform high-speed packet distribution.
  • This technical report describes design, implementation and evaluation of a hardware-accelerated system for distribution of network traffic among processor cores. The workload associated with network packet processing is split into several parts of similar size, and each core performs the required operation only on certain part of network packets. Packets of one flow are always processed by the same core. Hardware acceleration is used to perform high-speed packet distribution. (en)
Title
  • Hardware-accelerated distribution of network traffic among processor cores
  • Hardware-accelerated distribution of network traffic among processor cores (en)
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  • Hardware-accelerated distribution of network traffic among processor cores
  • Hardware-accelerated distribution of network traffic among processor cores (en)
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  • RIV/63839172:_____/10:00007041!RIV11-MSM-63839172
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  • 261218
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  • RIV/63839172:_____/10:00007041
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  • DMA; PCI Express; Multi-Core; FPGA; VHDL (en)
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  • [C7033E699629]
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  • Martínek, Tomáš
  • Puš, Viktor
  • Dedek, Tomáš
http://linked.open...n/vavai/riv/zamer
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