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Description
  • This paper deals with design and implementation of the Priority Queues System (PQ) for network devices using Field-Programmable Gate Arrays (FPGA). PQ provides input records storage and forwarding to multiple output interfaces in order defined by priotity rules. The designed architecture has the following characteristics. It provides stored data administration in an external static memory, which is used to store an optional number of queues. All of them have a selectable length and they can be optionaly placed in the memory. The queues can be distributed into several groups without any restrictions. Each group is assigned to one output interface. Every queue in the group has its optional priority. The component is designed to ensure a good throughput and it must be working on a required clock frequency. The Priority Queues system has been implemented and tested on COMBO6 card, which has been developed by the Liberouter project.
  • This paper deals with design and implementation of the Priority Queues System (PQ) for network devices using Field-Programmable Gate Arrays (FPGA). PQ provides input records storage and forwarding to multiple output interfaces in order defined by priotity rules. The designed architecture has the following characteristics. It provides stored data administration in an external static memory, which is used to store an optional number of queues. All of them have a selectable length and they can be optionaly placed in the memory. The queues can be distributed into several groups without any restrictions. Each group is assigned to one output interface. Every queue in the group has its optional priority. The component is designed to ensure a good throughput and it must be working on a required clock frequency. The Priority Queues system has been implemented and tested on COMBO6 card, which has been developed by the Liberouter project. (en)
  • Tato práce se zabývá návrhem a implementací systému prioritních front v programovatelném hradlovém poli (FPGA). Úkolem prioritních front je ukládat vstupní záznamy a předávat je několika výstupním rozhraním v pořadí určeném prioritnímy pravidly. Navržená architektura má následující vlastnosti. Poskytuje správu uložených dat v externí statické paměti, kterou využívá k uložení konfigurovatelného počtu front. Všechny mají volitelnou délku a lze je libovolně v této paměti rozložit. Fronty lze bez omezení rozdělit do několika skupin – každá skupina náleží jinému výstupnímu rozhraní. V této skupině jsou pak frontám libovolně přiřazeny jejich priority. Komponenta je navržena s ohledem na dobrou propustnost a musí fungovat na potřebné pracovní frekvenci. Systém prioritních front byl implementován a ověřen na kartě COMBO6, která je vyvíjena v rámci projektu Liberouter. (cs)
Title
  • Priority Queues System for Multi-gigabit Network Devices
  • Systém prioritních front pro multi-gigabitová síťová zařízení (cs)
  • Priority Queues System for Multi-gigabit Network Devices (en)
skos:prefLabel
  • Priority Queues System for Multi-gigabit Network Devices
  • Systém prioritních front pro multi-gigabitová síťová zařízení (cs)
  • Priority Queues System for Multi-gigabit Network Devices (en)
skos:notation
  • RIV/63839172:_____/05:00000110!RIV09-MSM-63839172
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • Z(MSM6383917201)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 538505
http://linked.open...ai/riv/idVysledku
  • RIV/63839172:_____/05:00000110
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • FIFO; LIFO; SIRO; Priority Queue; FIFO Priority; Systolic Field; FPGA; VHDL (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [31ADA12AF096]
http://linked.open...v/mistoKonaniAkce
  • Brno
http://linked.open...i/riv/mistoVydani
  • Brno
http://linked.open...i/riv/nazevZdroje
  • Proceedings of the International Interdisciplinary Honeywell EMI 2005 Student Competition and Conference
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Pazdera, Jan
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • VUT Brno FEKT, FIT, FSI
https://schema.org/isbn
  • 80-214-2942-9
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