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Description
  • This document concerns the development of the Combo6 card that aims at accelerating IPv6 and IPv4 routing. Three main processing blocks are distinguished in its architecture: packet parsing blocks, header matching blocks and output blocks. My work consists of several tools dealing with the simulation of packet parsing blocks. These tools provide possibilities for simulation, testing and developing algorithms for the hardware. Further, outputs of these tools may be used for simulation and testing of header matching blocks, even parallel simulation of packet parsing blocks and header matching blocks is possible.
  • This document concerns the development of the Combo6 card that aims at accelerating IPv6 and IPv4 routing. Three main processing blocks are distinguished in its architecture: packet parsing blocks, header matching blocks and output blocks. My work consists of several tools dealing with the simulation of packet parsing blocks. These tools provide possibilities for simulation, testing and developing algorithms for the hardware. Further, outputs of these tools may be used for simulation and testing of header matching blocks, even parallel simulation of packet parsing blocks and header matching blocks is possible. (en)
Title
  • Packet Analysis for IPv6 Router Implemented by a PCI Acceleration Card
  • Packet Analysis for IPv6 Router Implemented by a PCI Acceleration Card (en)
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  • Packet Analysis for IPv6 Router Implemented by a PCI Acceleration Card
  • Packet Analysis for IPv6 Router Implemented by a PCI Acceleration Card (en)
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  • RIV/63839172:_____/03:00000071!RIV/2004/MSM/000004/N
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  • 620223
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  • RIV/63839172:_____/03:00000071
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  • IPv6;router;packet;packet parsing;simulation;VHDL;nanoprocessor;Liberouter;Combo6;nsim;nanoprocessor assembler;HFE;header field extractor (en)
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  • [7F76E8CF4A4B]
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  • Brno
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  • CESNET z.s.p.o.
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  • Höfer, Filip
http://linked.open...rzeVyzkumneZpravy
  • CESNET technical report number 5/2003
http://linked.open...n/vavai/riv/zamer
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