About: Efficient VHDL Implementation of Symbol Synchronization for Software Radio based on FPGA

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

Attributes	Values
rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
rdfs:seeAlso	http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6868819
Description	The increasing popularity of Software Defined Radio is forcing complex digital signal processing blocks to be implemented in parallel design flow on FPGA or ASIC. One of the main sections of digital receiver is symbol synchronization block. The goal of this paper is to develop efficient Non-Data-Aided (NDA) feedback PLL-based synchronization scheme in VHDL language for RTL synthesis on FPGA. The first part of this paper is focused on formulation Maximum Likelihood (ML) criterion for timing error detector. This approach forms basic assumptions for derivation of the other timing error detectors like Zero-Crossing detector. The extensive emphasis will be put on simulation of synchronization models. This model is composed of interpolating filter, error timing detector and interpolation control block. The second part of this paper deals with simulation of proposed fully pipelined VHDL model and the results of RTL synthesis are discussed. The increasing popularity of Software Defined Radio is forcing complex digital signal processing blocks to be implemented in parallel design flow on FPGA or ASIC. One of the main sections of digital receiver is symbol synchronization block. The goal of this paper is to develop efficient Non-Data-Aided (NDA) feedback PLL-based synchronization scheme in VHDL language for RTL synthesis on FPGA. The first part of this paper is focused on formulation Maximum Likelihood (ML) criterion for timing error detector. This approach forms basic assumptions for derivation of the other timing error detectors like Zero-Crossing detector. The extensive emphasis will be put on simulation of synchronization models. This model is composed of interpolating filter, error timing detector and interpolation control block. The second part of this paper deals with simulation of proposed fully pipelined VHDL model and the results of RTL synthesis are discussed. (en)
Title	Efficient VHDL Implementation of Symbol Synchronization for Software Radio based on FPGA Efficient VHDL Implementation of Symbol Synchronization for Software Radio based on FPGA (en)
skos:prefLabel	Efficient VHDL Implementation of Symbol Synchronization for Software Radio based on FPGA Efficient VHDL Implementation of Symbol Synchronization for Software Radio based on FPGA (en)
skos:notation	RIV/49777513:23220/14:43921954!RIV15-MSM-23220___
http://linked.open...avai/riv/aktivita	S
http://linked.open...avai/riv/aktivity	S
http://linked.open...vai/riv/dodaniDat	2015
http://linked.open...aciTvurceVysledku	Fiala, Pavel Linhart, Richard
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Západočeská univerzita v Plzni / Fakulta elektrotechnická
http://linked.open...dnocenehoVysledku	13878
http://linked.open...ai/riv/idVysledku	RIV/49777513:23220/14:43921954
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	VHDL; symbol synchronization; signal; processing; SDR; FPGA; communication; digital (en)
http://linked.open.../riv/klicoveSlovo	VHDL SDR FPGA communication digital signal symbol synchronization processing
http://linked.open...ontrolniKodProRIV	[1970B930676A]
http://linked.open...v/mistoKonaniAkce	Varšava
http://linked.open...i/riv/mistoVydani	Varšava
http://linked.open...i/riv/nazevZdroje	Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems
http://linked.open...in/vavai/riv/obor	JA
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...UplatneniVysledku	2014
http://linked.open...iv/tvurceVysledku	Fiala, Pavel Linhart, Richard
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open...ain/vavai/riv/wos	000346734200069
http://linked.open.../riv/zahajeniAkce	2014-04-23 (xsd:date)
number of pages	4 (xsd:int)
http://bibframe.org/vocab/doi	10.1109/DDECS.2014.6868819
http://purl.org/ne...btex#hasPublisher	IEEE (The Institute of Electrical and Electronics Engineers)
https://schema.org/isbn	978-1-4799-4558-0
http://localhost/t...ganizacniJednotka	23220

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