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Description
| - This paper describes design of a new hard- ware platform (interface) specially designed to fit re- quirements for control of multi-level converters (MLC) with high number of switching devices. The new de- signed platform is backward compatible with DSP-based controllers currently used in research projects at RICE while brings many improvements linked mainly to a new concept utilizing a universal field programmable gate array (FPGA). Thus, the new MLC interface combines benefits of a powerful microcontroller with a DSP core, flexible FPGA Cyclone III and redesigned analog circuits with external bipolar precise A/D converters. It opens new possibilities not only for control of new MLC topologies under research, but also for advanced model- based control and estimation strategies.
- This paper describes design of a new hard- ware platform (interface) specially designed to fit re- quirements for control of multi-level converters (MLC) with high number of switching devices. The new de- signed platform is backward compatible with DSP-based controllers currently used in research projects at RICE while brings many improvements linked mainly to a new concept utilizing a universal field programmable gate array (FPGA). Thus, the new MLC interface combines benefits of a powerful microcontroller with a DSP core, flexible FPGA Cyclone III and redesigned analog circuits with external bipolar precise A/D converters. It opens new possibilities not only for control of new MLC topologies under research, but also for advanced model- based control and estimation strategies. (en)
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Title
| - Multi-level Converter Interface - A New Hardware Platform For Multi-level Converters Development
- Multi-level Converter Interface - A New Hardware Platform For Multi-level Converters Development (en)
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skos:prefLabel
| - Multi-level Converter Interface - A New Hardware Platform For Multi-level Converters Development
- Multi-level Converter Interface - A New Hardware Platform For Multi-level Converters Development (en)
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skos:notation
| - RIV/49777513:23220/12:43915546!RIV13-MSM-23220___
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http://linked.open...avai/riv/aktivita
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http://linked.open...avai/riv/aktivity
| - P(ED2.1.00/03.0094), P(TA01010863), S
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http://linked.open...vai/riv/dodaniDat
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http://linked.open...aciTvurceVysledku
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http://linked.open.../riv/druhVysledku
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http://linked.open...iv/duvernostUdaju
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http://linked.open...titaPredkladatele
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http://linked.open...dnocenehoVysledku
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http://linked.open...ai/riv/idVysledku
| - RIV/49777513:23220/12:43915546
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http://linked.open...riv/jazykVysledku
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http://linked.open.../riv/klicovaSlova
| - memory mapped devices; CPLD; Complex Programmable Logic Device; FPGA; Field Programmable Gate Array; Multi-level converter (en)
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http://linked.open.../riv/klicoveSlovo
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http://linked.open...ontrolniKodProRIV
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http://linked.open...v/mistoKonaniAkce
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http://linked.open...i/riv/mistoVydani
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http://linked.open...i/riv/nazevZdroje
| - 2012 International Conference on Applied Electronics
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http://linked.open...in/vavai/riv/obor
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http://linked.open...ichTvurcuVysledku
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http://linked.open...cetTvurcuVysledku
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http://linked.open...vavai/riv/projekt
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http://linked.open...UplatneniVysledku
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http://linked.open...iv/tvurceVysledku
| - Glasberger, Tomáš
- Košan, Tomáš
- Peroutka, Zdeněk
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http://linked.open...vavai/riv/typAkce
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http://linked.open.../riv/zahajeniAkce
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issn
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number of pages
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http://purl.org/ne...btex#hasPublisher
| - Západočeská univerzita v Plzni
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https://schema.org/isbn
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http://localhost/t...ganizacniJednotka
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