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Description
  • This paper describes design of a new hard- ware platform (interface) specially designed to fit re- quirements for control of multi-level converters (MLC) with high number of switching devices. The new de- signed platform is backward compatible with DSP-based controllers currently used in research projects at RICE while brings many improvements linked mainly to a new concept utilizing a universal field programmable gate array (FPGA). Thus, the new MLC interface combines benefits of a powerful microcontroller with a DSP core, flexible FPGA Cyclone III and redesigned analog circuits with external bipolar precise A/D converters. It opens new possibilities not only for control of new MLC topologies under research, but also for advanced model- based control and estimation strategies.
  • This paper describes design of a new hard- ware platform (interface) specially designed to fit re- quirements for control of multi-level converters (MLC) with high number of switching devices. The new de- signed platform is backward compatible with DSP-based controllers currently used in research projects at RICE while brings many improvements linked mainly to a new concept utilizing a universal field programmable gate array (FPGA). Thus, the new MLC interface combines benefits of a powerful microcontroller with a DSP core, flexible FPGA Cyclone III and redesigned analog circuits with external bipolar precise A/D converters. It opens new possibilities not only for control of new MLC topologies under research, but also for advanced model- based control and estimation strategies. (en)
Title
  • Multi-level Converter Interface - A New Hardware Platform For Multi-level Converters Development
  • Multi-level Converter Interface - A New Hardware Platform For Multi-level Converters Development (en)
skos:prefLabel
  • Multi-level Converter Interface - A New Hardware Platform For Multi-level Converters Development
  • Multi-level Converter Interface - A New Hardware Platform For Multi-level Converters Development (en)
skos:notation
  • RIV/49777513:23220/12:43915546!RIV13-MSM-23220___
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(ED2.1.00/03.0094), P(TA01010863), S
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 152373
http://linked.open...ai/riv/idVysledku
  • RIV/49777513:23220/12:43915546
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • memory mapped devices; CPLD; Complex Programmable Logic Device; FPGA; Field Programmable Gate Array; Multi-level converter (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [91E11FE3787F]
http://linked.open...v/mistoKonaniAkce
  • Plzeň
http://linked.open...i/riv/mistoVydani
  • Plzeň
http://linked.open...i/riv/nazevZdroje
  • 2012 International Conference on Applied Electronics
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Glasberger, Tomáš
  • Košan, Tomáš
  • Peroutka, Zdeněk
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
issn
  • 1803-7232
number of pages
http://purl.org/ne...btex#hasPublisher
  • Západočeská univerzita v Plzni
https://schema.org/isbn
  • 978-80-261-0038-6
http://localhost/t...ganizacniJednotka
  • 23220
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