About: Test Pattern Compression for Circuits with the RESPIN Architecture

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	The test pattern compaction method combined with test input data compression technique for the RESPIN architecture is presented. RESPIN architecture is compatible with the IEEE 1500 standard and can be implemented in complex SoCs. The test pattern compaction method combined with test input data compression technique for the RESPIN architecture is presented. RESPIN architecture is compatible with the IEEE 1500 standard and can be implemented in complex SoCs. (en) Článek představuje kompaktní metodu s kombinací kompresní techniky, která připravuje komprimované testovací vzorky pro RESPIN architekturu. RESPIN architektura je kompatibilní se standardem IEEE 1500. (cs)
Title	Test Pattern Compression for Circuits with the RESPIN Architecture Komprese testovacích vzorků pro obvody s RESPIN architekturou (cs) Test Pattern Compression for Circuits with the RESPIN Architecture (en)
skos:prefLabel	Test Pattern Compression for Circuits with the RESPIN Architecture Komprese testovacích vzorků pro obvody s RESPIN architekturou (cs) Test Pattern Compression for Circuits with the RESPIN Architecture (en)
skos:notation	RIV/46747885:24220/05:00000136!RIV06-GA0-24220___
http://linked.open.../vavai/riv/strany	141-146
http://linked.open...avai/riv/aktivita	P
http://linked.open...avai/riv/aktivity	P(GA102/04/2137)
http://linked.open...vai/riv/dodaniDat	2006
http://linked.open...aciTvurceVysledku	Zahrádka, Jiří Novák, Ondřej
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Technická univerzita v Liberci / Fakulta mechatroniky, informatiky a mezioborových studií
http://linked.open...dnocenehoVysledku	546462
http://linked.open...ai/riv/idVysledku	RIV/46747885:24220/05:00000136
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	COMPAS; RESPIN; Scan Chain; Testability (en)
http://linked.open.../riv/klicoveSlovo	RESPIN Testability COMPAS Scan Chain
http://linked.open...ontrolniKodProRIV	[13B3CCF10B13]
http://linked.open...v/mistoKonaniAkce	Tallinn, Estonia
http://linked.open...i/riv/mistoVydani	Tallinn, Estonia
http://linked.open...i/riv/nazevZdroje	Informal Digest of Papers of the 10th IEEE European Test Symposium
http://linked.open...in/vavai/riv/obor	JA
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...vavai/riv/projekt	Design of highly reliable control systems built on dynamically reconfigurable FPGAs.
http://linked.open...UplatneniVysledku	2005
http://linked.open...iv/tvurceVysledku	Novák, Ondřej Zahrádka, Jiří
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2005-05-22 (xsd:date)
number of pages	6 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Neuveden
https://schema.org/isbn	83-919289-9-3
http://localhost/t...ganizacniJednotka	24220

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