About: COMPAS - Compressed test pattern sequencer for scan based circuits

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	This paper presents a software tool for test pattern compaction combined with compression of the test patterns to further reduce test data volume and time requirement. Usually the test set compaction is performed independently on test compression. We have implemented a test compaction and compression scheme that reorders test patterns previously generated in an ATPG in such a way that they are well suited for decompression. The compressed test sequence is decompressed in a scan chain. No design changes are required to be done in the functional part of the circuit. The tool is called COMPAS and it finds a sequence of overlapping patterns; each pattern detects a maximum number of circuit faults. This paper presents a software tool for test pattern compaction combined with compression of the test patterns to further reduce test data volume and time requirement. Usually the test set compaction is performed independently on test compression. We have implemented a test compaction and compression scheme that reorders test patterns previously generated in an ATPG in such a way that they are well suited for decompression. The compressed test sequence is decompressed in a scan chain. No design changes are required to be done in the functional part of the circuit. The tool is called COMPAS and it finds a sequence of overlapping patterns; each pattern detects a maximum number of circuit faults. (en)
Title	COMPAS - Compressed test pattern sequencer for scan based circuits COMPAS - Compressed test pattern sequencer for scan based circuits (en)
skos:prefLabel	COMPAS - Compressed test pattern sequencer for scan based circuits COMPAS - Compressed test pattern sequencer for scan based circuits (en)
skos:notation	RIV/46747885:24220/05:#0001346!RIV10-GA0-24220___
http://linked.open...avai/riv/aktivita	P
http://linked.open...avai/riv/aktivity	P(1QS108040510), P(GA102/04/2137)
http://linked.open...vai/riv/dodaniDat	2010
http://linked.open...aciTvurceVysledku	Novák, Ondřej Plíva, Zdeněk
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Technická univerzita v Liberci / Fakulta mechatroniky, informatiky a mezioborových studií
http://linked.open...dnocenehoVysledku	515963
http://linked.open...ai/riv/idVysledku	RIV/46747885:24220/05:#0001346
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Scan Chain (en)
http://linked.open.../riv/klicoveSlovo	Scan Chain
http://linked.open...ontrolniKodProRIV	[16F4E23FEAA6]
http://linked.open...v/mistoKonaniAkce	Budapest, HUNGARY
http://linked.open...i/riv/mistoVydani	Budapest, HUNGARY
http://linked.open...i/riv/nazevZdroje	DEPENDABLE COMPUTING - EDCC-5, PROCEEDINGS
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...vavai/riv/projekt	Technology for improving the testability of modern digital circuits Design of highly reliable control systems built on dynamically reconfigurable FPGAs.
http://linked.open...UplatneniVysledku	2005
http://linked.open...iv/tvurceVysledku	Novák, Ondřej Plíva, Zdeněk
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2005-01-01 (xsd:date)
issn	0302-9743
number of pages	12 (xsd:int)
http://purl.org/ne...btex#hasPublisher	SPRINGER-VERLAG BERLIN
https://schema.org/isbn	3-540-25723-3
http://localhost/t...ganizacniJednotka	24220

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