About: Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area

Facets (new session)
Description
Metadata
Settings
- owl:sameAs
- Inference Rule:

About: Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area Goto Sponge NotDistinct Permalink

An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

Attributes	Values
rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	The paper presents a methodology of fault tolerant system design into an FPGA with the ability of the transient fault and the permanent fault mitigation. The transient fault mitigation is done by the partial dynamic reconfiguration. The mitigation of a certain number of permanent faults is based on using a specific fault tolerant architecture occupiing less resources than the previosly used one and excluding the faulty part of the FPGA. This inovative technique is based on the precompiled configurations stored in an external memory. To reduce the required space for a partial bitstream the relocation technique is used. The paper presents a methodology of fault tolerant system design into an FPGA with the ability of the transient fault and the permanent fault mitigation. The transient fault mitigation is done by the partial dynamic reconfiguration. The mitigation of a certain number of permanent faults is based on using a specific fault tolerant architecture occupiing less resources than the previosly used one and excluding the faulty part of the FPGA. This inovative technique is based on the precompiled configurations stored in an external memory. To reduce the required space for a partial bitstream the relocation technique is used. (en)
Title	Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area (en)
skos:prefLabel	Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area (en)
skos:notation	RIV/00216305:26230/13:PU106378!RIV14-MSM-26230___
http://linked.open...avai/riv/aktivita	P S Z
http://linked.open...avai/riv/aktivity	P(ED1.1.00/02.0070), P(LD12036), S, Z(MSM0021630528)
http://linked.open...vai/riv/dodaniDat	2014
http://linked.open...aciTvurceVysledku	Straka, Martin Kotásek, Zdeněk Mičulka, Lukáš
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	87593
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/13:PU106378
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	methodology, partial dynamic reconfiguration, relocation, synchronization, limited redundant space (en)
http://linked.open.../riv/klicoveSlovo	relocation methodology limited redundant space partial dynamic reconfiguration synchronization
http://linked.open...ontrolniKodProRIV	[92FCF5507E69]
http://linked.open...v/mistoKonaniAkce	Santander
http://linked.open...i/riv/mistoVydani	Santander
http://linked.open...i/riv/nazevZdroje	16th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
http://linked.open...in/vavai/riv/obor	IN
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...vavai/riv/projekt	Methodologies for Fault Tolerant Systems Design Development, Implementation and Verification IT4Innovations Centre of Excellence
http://linked.open...UplatneniVysledku	2013
http://linked.open...iv/tvurceVysledku	Kotásek, Zdeněk Straka, Martin Mičulka, Lukáš
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2013-09-04 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Výzkum informačních technologií z hlediska bezpečnosti
number of pages	8 (xsd:int)
http://purl.org/ne...btex#hasPublisher	IEEE Computer Society
https://schema.org/isbn	978-0-7695-5074-9
http://localhost/t...ganizacniJednotka	26230

Faceted Search & Find service v1.16.118 as of Jun 21 2024

Alternative Linked Data Documents: ODE Content Formats:

RDF

ODATA

Microdata

About

OpenLink Virtuoso version 07.20.3240 as of Jun 21 2024, on Linux (x86_64-pc-linux-gnu), Single-Server Edition (126 GB total memory, 112 GB memory in use)
Data on this page belongs to its respective rights holders.
Virtuoso Faceted Browser Copyright © 2009-2024 OpenLink Software