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  • As the complexity of current hardware systems rises rapidly, it is a challenging task to harden these systems against faults and to complete their verification and manufacturing test. Not only that verification and testing take a considerable amount of time but the number of design errors, faults, manufacturing defects and crosstalks increases with the rising complexity as well. Furthermore, when a system is designed to be reliable new issues come into play making the picture even more complex. In this paper we performed a detailed analysis of two approaches devoted to verification of hardened systems, with respect to the test set generation: the first one is based on classical Automatic Test Pattern Generation, the second one on Constrained-random Stimulus Generation. We evaluated their qualities as well as their drawbacks and introduced few ideas about their combination in order to create a new promising approach for verification of reliable systems.
  • As the complexity of current hardware systems rises rapidly, it is a challenging task to harden these systems against faults and to complete their verification and manufacturing test. Not only that verification and testing take a considerable amount of time but the number of design errors, faults, manufacturing defects and crosstalks increases with the rising complexity as well. Furthermore, when a system is designed to be reliable new issues come into play making the picture even more complex. In this paper we performed a detailed analysis of two approaches devoted to verification of hardened systems, with respect to the test set generation: the first one is based on classical Automatic Test Pattern Generation, the second one on Constrained-random Stimulus Generation. We evaluated their qualities as well as their drawbacks and introduced few ideas about their combination in order to create a new promising approach for verification of reliable systems. (en)
Title
  • Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability
  • Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability (en)
skos:prefLabel
  • Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability
  • Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability (en)
skos:notation
  • RIV/00216305:26230/13:PU106327!RIV14-MSM-26230___
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(ED1.1.00/02.0070), P(LD12036), S, Z(MSM0021630528)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
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  • 60454
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26230/13:PU106327
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • ATPG, funkční verifikace. (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [5E3D0D83054C]
http://linked.open...v/mistoKonaniAkce
  • Karlovy Vary
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  • Karlovy Vary
http://linked.open...i/riv/nazevZdroje
  • IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems
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http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Kotásek, Zdeněk
  • Šimková, Marcela
  • Bolchini, Cristiana
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
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  • IEEE Computer Society
https://schema.org/isbn
  • 978-1-4673-6133-0
http://localhost/t...ganizacniJednotka
  • 26230
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