About: On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems

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About: On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems Goto Sponge NotDistinct Permalink

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	The paper details design of a hardware unit for preventing real-time systems from overloads caused by excessive interrupt rates. Novelty of the hardware can be seen in the fact it is able to adapt interrupt service rate to the RT system load and to the actual priority assignment policy. The load is monitored on basis of special low-overhead signals produced by the system for this purpose. The hardware is designed to preprocess all interrupts before they arrive to the system. The hardware is ready to buffer each interrupt-related communication until the system is underloaded or running an activity having a lower priority comparing to the interrupt. Design of the hardware was described in VHDL and synthesized into Xilinx Spartan-6 devices. Details such as buiding blocks, overheads and limits related to the realization are presented in this paper. The paper details design of a hardware unit for preventing real-time systems from overloads caused by excessive interrupt rates. Novelty of the hardware can be seen in the fact it is able to adapt interrupt service rate to the RT system load and to the actual priority assignment policy. The load is monitored on basis of special low-overhead signals produced by the system for this purpose. The hardware is designed to preprocess all interrupts before they arrive to the system. The hardware is ready to buffer each interrupt-related communication until the system is underloaded or running an activity having a lower priority comparing to the interrupt. Design of the hardware was described in VHDL and synthesized into Xilinx Spartan-6 devices. Details such as buiding blocks, overheads and limits related to the realization are presented in this paper. (en)
Title	On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems (en)
skos:prefLabel	On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems (en)
skos:notation	RIV/00216305:26230/13:PU106278!RIV14-MSM-26230___
http://linked.open...avai/riv/aktivita	P S Z
http://linked.open...avai/riv/aktivity	P(7H10013), P(ED1.1.00/02.0070), S, Z(MSM0021630528)
http://linked.open...vai/riv/dodaniDat	2014
http://linked.open...aciTvurceVysledku	Strnadel, Josef
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	93683
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/13:PU106278
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	task, operating system, load monitoring, interrupt control, scheduling, overload prevention, priority space (en)
http://linked.open.../riv/klicoveSlovo	interrupt control load monitoring overload prevention priority space task scheduling operating system
http://linked.open...ontrolniKodProRIV	[534E15071D2C]
http://linked.open...v/mistoKonaniAkce	Karlovy Vary
http://linked.open...i/riv/mistoVydani	Brno
http://linked.open...i/riv/nazevZdroje	Proceedings of the IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	1 (xsd:int)
http://linked.open...cetTvurcuVysledku	1 (xsd:int)
http://linked.open...vavai/riv/projekt	Reduced Certification Costs for Trusted Multi-core Platforms IT4Innovations Centre of Excellence
http://linked.open...UplatneniVysledku	2013
http://linked.open...iv/tvurceVysledku	Strnadel, Josef
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2013-04-08 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Výzkum informačních technologií z hlediska bezpečnosti
number of pages	6 (xsd:int)
http://bibframe.org/vocab/doi	10.1109/DDECS.2013.6549783
http://purl.org/ne...btex#hasPublisher	IEEE Computer Society
https://schema.org/isbn	978-1-4673-6133-0
http://localhost/t...ganizacniJednotka	26230

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