About: HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	Functional verification is a widespread technique to check whether a hardware system satisfies a given correctness specification. As the complexity of modern hardware systems rises rapidly, it is a challenging task to find appropriate techniques for acceleration of this process. In this paper we present HAVEN, a freely available open functional verification framework that exploits the field-programmable gate array (FPGA) technology for cycle-accurate acceleration of simulation-based verification runs. HAVEN takes advantage of the inherent parallelism of hardware systems and moves the verified system together with transaction-based interface components of the functional verification environment from software into an FPGA. The presented framework is written in SystemVerilog and complies with the principles of functional verification methodologies (OVM, UVM), assertion-based verification, and also provides adequate debugging visibility, making its application range quite large. Our experiment Functional verification is a widespread technique to check whether a hardware system satisfies a given correctness specification. As the complexity of modern hardware systems rises rapidly, it is a challenging task to find appropriate techniques for acceleration of this process. In this paper we present HAVEN, a freely available open functional verification framework that exploits the field-programmable gate array (FPGA) technology for cycle-accurate acceleration of simulation-based verification runs. HAVEN takes advantage of the inherent parallelism of hardware systems and moves the verified system together with transaction-based interface components of the functional verification environment from software into an FPGA. The presented framework is written in SystemVerilog and complies with the principles of functional verification methodologies (OVM, UVM), assertion-based verification, and also provides adequate debugging visibility, making its application range quite large. Our experiment (en)
Title	HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware (en)
skos:prefLabel	HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware (en)
skos:notation	RIV/00216305:26230/12:PU96138!RIV13-GA0-26230___
http://linked.open...avai/riv/aktivita	P S Z
http://linked.open...avai/riv/aktivity	P(7H10013), P(GAP103/10/0306), P(OC10009), S, Z(MSM0021630528)
http://linked.open...iv/cisloPeriodika	7261
http://linked.open...vai/riv/dodaniDat	2013
http://linked.open...aciTvurceVysledku	Lengál, Ondřej Kajan, Michal Šimková, Marcela
http://linked.open.../riv/druhVysledku	J - Článek v odborném periodiku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	138678
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/12:PU96138
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	functional verification, testbench, SystemVerilog, hardware acceleration, FPGA (en)
http://linked.open.../riv/klicoveSlovo	FPGA SystemVerilog functional verification hardware acceleration testbench
http://linked.open...odStatuVydavatele	DE - Spolková republika Německo
http://linked.open...ontrolniKodProRIV	[21C056AB1F5A]
http://linked.open...i/riv/nazevZdroje	Lecture Notes in Computer Science
http://linked.open...in/vavai/riv/obor	IN
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...vavai/riv/projekt	Reduced Certification Costs for Trusted Multi-core Platforms Static and Dynamic Verification of Programs with Advanced Features of Concurrency and Unboundedness Dealing with Complex Data Structures and Concurrency within the Rich Model Toolkit
http://linked.open...UplatneniVysledku	2012
http://linked.open...v/svazekPeriodika	2012
http://linked.open...iv/tvurceVysledku	Kajan, Michal Lengál, Ondřej Šimková, Marcela
http://linked.open...n/vavai/riv/zamer	Výzkum informačních technologií z hlediska bezpečnosti
issn	0302-9743
number of pages	7 (xsd:int)
http://localhost/t...ganizacniJednotka	26230

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