About: Reflecting RTOS Model During WCET Timing Analysis: MSP430/FreeRTOS Case Study     Goto   Sponge   NotDistinct   Permalink

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  • The determination of the execution time upper bound, commonly called Worst-Case Execution Time (WCET), is a necessary step in the development and validation process for real-time systems. The WCET analysis techniques can be classified as static or dynamic. While a high-level language code suffices for the static techniques, for a precise WCET analysis a target architecture or its authentic simulator able to run the final machine-level code of an analyzed application is needed by the dynamic techniques. In the paper, we have decided not only to present a novel hybrid timing analysis technique, but also to show its practical applicability in the area of WCET analysis over particular embedded architecture (MSP430) and real-time operating system (FreeRTOS). Novelty of the presented method can be seen in the fact the operating system model is reflected during the analysis in order to facilitate the process of derivating schedulability test formulas, create detail task/stack analysis etc. Applic
  • The determination of the execution time upper bound, commonly called Worst-Case Execution Time (WCET), is a necessary step in the development and validation process for real-time systems. The WCET analysis techniques can be classified as static or dynamic. While a high-level language code suffices for the static techniques, for a precise WCET analysis a target architecture or its authentic simulator able to run the final machine-level code of an analyzed application is needed by the dynamic techniques. In the paper, we have decided not only to present a novel hybrid timing analysis technique, but also to show its practical applicability in the area of WCET analysis over particular embedded architecture (MSP430) and real-time operating system (FreeRTOS). Novelty of the presented method can be seen in the fact the operating system model is reflected during the analysis in order to facilitate the process of derivating schedulability test formulas, create detail task/stack analysis etc. Applic (en)
Title
  • Reflecting RTOS Model During WCET Timing Analysis: MSP430/FreeRTOS Case Study
  • Reflecting RTOS Model During WCET Timing Analysis: MSP430/FreeRTOS Case Study (en)
skos:prefLabel
  • Reflecting RTOS Model During WCET Timing Analysis: MSP430/FreeRTOS Case Study
  • Reflecting RTOS Model During WCET Timing Analysis: MSP430/FreeRTOS Case Study (en)
skos:notation
  • RIV/00216305:26230/12:PU103010!RIV13-MSM-26230___
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(ED1.1.00/02.0070), S, Z(MSM0021630528)
http://linked.open...iv/cisloPeriodika
  • 4
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 164540
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26230/12:PU103010
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • analysis, assembly, compiler, FreeRTOS, model, MSPsim, MSP430, operating system, profiler, real time, response time, simulator, worst case, execution time (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...odStatuVydavatele
  • SK - Slovenská republika
http://linked.open...ontrolniKodProRIV
  • [08DC4CAD2903]
http://linked.open...i/riv/nazevZdroje
  • Acta Electrotechnica et Informatica
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...v/svazekPeriodika
  • 12
http://linked.open...iv/tvurceVysledku
  • Strnadel, Josef
  • Rajnoha, Peter
http://linked.open...n/vavai/riv/zamer
issn
  • 1335-8243
number of pages
http://bibframe.org/vocab/doi
  • 10.2478/v10198-012-0041-3
http://localhost/t...ganizacniJednotka
  • 26230
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