About: Low-Latency Modular Packet Header Parser for FPGA     Goto   Sponge   NotDistinct   Permalink

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Description
  • Packet parsing is the basic operation performed at all points of the network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules, however the high-speed parsers often use very large chip area. We propose novel architecture of pipelined packet parser, which in addition to high throughput (over 100 Gb/s) offers also low latency. Moreover, the latency to throughput ratio can be finely tuned to fit the particular application. The parser is handoptimized thanks to the direct implementation in VHDL, yet the structure is very uniform and easily extensible for new protocols.
  • Packet parsing is the basic operation performed at all points of the network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules, however the high-speed parsers often use very large chip area. We propose novel architecture of pipelined packet parser, which in addition to high throughput (over 100 Gb/s) offers also low latency. Moreover, the latency to throughput ratio can be finely tuned to fit the particular application. The parser is handoptimized thanks to the direct implementation in VHDL, yet the structure is very uniform and easily extensible for new protocols. (en)
Title
  • Low-Latency Modular Packet Header Parser for FPGA
  • Low-Latency Modular Packet Header Parser for FPGA (en)
skos:prefLabel
  • Low-Latency Modular Packet Header Parser for FPGA
  • Low-Latency Modular Packet Header Parser for FPGA (en)
skos:notation
  • RIV/00216305:26230/12:PU101888!RIV13-MSM-26230___
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(ED1.1.00/02.0070), P(LM2010005), S, Z(MSM0021630528)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 147527
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26230/12:PU101888
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • Packet Parsing, Latency, FPGA (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [F05397F0DACB]
http://linked.open...v/mistoKonaniAkce
  • Austin, TX
http://linked.open...i/riv/mistoVydani
  • Austin
http://linked.open...i/riv/nazevZdroje
  • ACM/IEEE Symposium on Architectures for Networking and Communications Systems
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
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http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Kořenek, Jan
  • Puš, Viktor
  • Kekely, Lukáš
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • Association for Computing Machinery
https://schema.org/isbn
  • 978-1-4503-1685-9
http://localhost/t...ganizacniJednotka
  • 26230
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