About: On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits

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About: On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits Goto Sponge NotDistinct Permalink

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	Major drawback of high level design methodologies such as RTL can be seen in the following facts. First, they lack of sufficiently precise fault models - compared to sophisticated models available for low level description levels such as logic gate level. Second, since the structure of a design changes significantly with every logic synthesis run, testability analysis is typically performed only after final logic synthesis. As a consequence, results of the analysis could be obtained when it is very costly to reflect them in the high level design. The drawbacks can be removed in several ways. In the contribution, it is supposed the analysis is performed at RTL and is efficient enough to be run after each change in RTL design - giving a designer an immediate information about the change impact to testability parameters. Under the assumption, following requirements are posed to the analysis: low computational complexity and accuracy. The latter requirement is met if strong correlation is det Major drawback of high level design methodologies such as RTL can be seen in the following facts. First, they lack of sufficiently precise fault models - compared to sophisticated models available for low level description levels such as logic gate level. Second, since the structure of a design changes significantly with every logic synthesis run, testability analysis is typically performed only after final logic synthesis. As a consequence, results of the analysis could be obtained when it is very costly to reflect them in the high level design. The drawbacks can be removed in several ways. In the contribution, it is supposed the analysis is performed at RTL and is efficient enough to be run after each change in RTL design - giving a designer an immediate information about the change impact to testability parameters. Under the assumption, following requirements are posed to the analysis: low computational complexity and accuracy. The latter requirement is met if strong correlation is det (en)
Title	On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits (en)
skos:prefLabel	On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits (en)
skos:notation	RIV/00216305:26230/11:PU96050!RIV12-MSM-26230___
http://linked.open...avai/riv/aktivita	P S
http://linked.open...avai/riv/aktivity	P(GA102/09/1668), S
http://linked.open...vai/riv/dodaniDat	2012
http://linked.open...aciTvurceVysledku	Strnadel, Josef Rumplík, Michal
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	218123
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/11:PU96050
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	testability, fault coverage, stuck at fault, register transfer level, correlation, scan, digital, circuit (en)
http://linked.open.../riv/klicoveSlovo	circuit fault coverage register transfer level scan stuck at fault testability correlation digital
http://linked.open...ontrolniKodProRIV	[61C0A77006DA]
http://linked.open...v/mistoKonaniAkce	Oulu
http://linked.open...i/riv/mistoVydani	Oulu
http://linked.open...i/riv/nazevZdroje	Proceedings of the 14th Euromicro Conference on Digital System Design - Architectures, Methods and Tools 2011
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...vavai/riv/projekt	SoC circuits reliability and availability improvement
http://linked.open...UplatneniVysledku	2011
http://linked.open...iv/tvurceVysledku	Strnadel, Josef Rumplík, Michal
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2011-08-31 (xsd:date)
number of pages	8 (xsd:int)
http://purl.org/ne...btex#hasPublisher	IEEE Computer Society
https://schema.org/isbn	978-0-7695-4494-6
http://localhost/t...ganizacniJednotka	26230

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