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  • In the paper, a technique for design of highly dependable communication structure in SRAM-based FPGA is presented. The architecture of the multicore system and the structure of fault tolerant bus with cache memories are demonstrated. The fault tolerant properties are achieved by the replication and utilization of the self checking techniques together with partial dynamic reconfiguration. The experimental results show that presented system has small overhead if the high number of function units are used in the dependable system. All experiments were done on the Virtex5 and Virtex6 platform.
  • In the paper, a technique for design of highly dependable communication structure in SRAM-based FPGA is presented. The architecture of the multicore system and the structure of fault tolerant bus with cache memories are demonstrated. The fault tolerant properties are achieved by the replication and utilization of the self checking techniques together with partial dynamic reconfiguration. The experimental results show that presented system has small overhead if the high number of function units are used in the dependable system. All experiments were done on the Virtex5 and Virtex6 platform. (en)
Title
  • Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA
  • Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA (en)
skos:prefLabel
  • Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA
  • Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA (en)
skos:notation
  • RIV/00216305:26230/11:PU95980!RIV13-MSM-26230___
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GA102/09/1668), S, Z(MSM0021630528)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 184721
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26230/11:PU95980
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • FPGA, fault tolerant, bus, multicore, reconfiguration, on-line checker, TMR (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [CBB087724218]
http://linked.open...v/mistoKonaniAkce
  • Cottbus
http://linked.open...i/riv/mistoVydani
  • Cottbus
http://linked.open...i/riv/nazevZdroje
  • IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Kaštil, Jan
  • Kotásek, Zdeněk
  • Novotný, Jaroslav
  • Straka, Martin
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • IEEE Computer Society
https://schema.org/isbn
  • 978-1-4244-9753-9
http://localhost/t...ganizacniJednotka
  • 26230
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