About: Reduction of Power Dissipation Through Parallel Optimization of Test Vector and Scan Register Sequences

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	In the paper, novel method for reducing power dissipation during test application time is presented. When compared to existing methods, its advantage can be seen in the fact that power dissipation is evaluated by means of precise and fast simulation based metric rather than by means of commonly utilized simple metric based on evaluating Hamming distance between test vectors. In our method, the metric is evaluated over CMOS primitives from AMI technological libraries. In order to reduce power dissipation, the sequence of test vectors to be applied and proper ordering of registers within scan chains are optimized. In existing approaches, the optimizations are typically performed separately in a sequence because problems they correspond to are seen to be independent. On contrary to that, we have united the search spaces and solved these two problems as a single optimization task. Genetic algorithm operating over an appropriate encoding of the problem was utilized to optimize the problem. Proposed method In the paper, novel method for reducing power dissipation during test application time is presented. When compared to existing methods, its advantage can be seen in the fact that power dissipation is evaluated by means of precise and fast simulation based metric rather than by means of commonly utilized simple metric based on evaluating Hamming distance between test vectors. In our method, the metric is evaluated over CMOS primitives from AMI technological libraries. In order to reduce power dissipation, the sequence of test vectors to be applied and proper ordering of registers within scan chains are optimized. In existing approaches, the optimizations are typically performed separately in a sequence because problems they correspond to are seen to be independent. On contrary to that, we have united the search spaces and solved these two problems as a single optimization task. Genetic algorithm operating over an appropriate encoding of the problem was utilized to optimize the problem. Proposed method (en)
Title	Reduction of Power Dissipation Through Parallel Optimization of Test Vector and Scan Register Sequences Reduction of Power Dissipation Through Parallel Optimization of Test Vector and Scan Register Sequences (en)
skos:prefLabel	Reduction of Power Dissipation Through Parallel Optimization of Test Vector and Scan Register Sequences Reduction of Power Dissipation Through Parallel Optimization of Test Vector and Scan Register Sequences (en)
skos:notation	RIV/00216305:26230/10:PU89683!RIV11-GA0-26230___
http://linked.open...avai/riv/aktivita	P S Z
http://linked.open...avai/riv/aktivity	P(GA102/09/1668), P(GD102/09/H042), S, Z(MSM0021630528)
http://linked.open...vai/riv/dodaniDat	2011
http://linked.open...aciTvurceVysledku	Kotásek, Zdeněk Strnadel, Josef Škarvada, Jaroslav
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	284300
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/10:PU89683
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	test vector, scan chain, low power, power dissipation, optimization, genetic algorithm, CMOS, AMI, ordering (en)
http://linked.open.../riv/klicoveSlovo	low power CMOS AMI genetic algorithm optimization scan chain ordering power dissipation test vector
http://linked.open...ontrolniKodProRIV	[21DFED89DB6B]
http://linked.open...v/mistoKonaniAkce	Vienna
http://linked.open...i/riv/mistoVydani	Vienna
http://linked.open...i/riv/nazevZdroje	Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...vavai/riv/projekt	SoC circuits reliability and availability improvement Mathematical and Engineering Approaches to Developing Reliable and Secure Concurrent and Distributed Computer Systems
http://linked.open...UplatneniVysledku	2010
http://linked.open...iv/tvurceVysledku	Kotásek, Zdeněk Strnadel, Josef Škarvada, Jaroslav
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2010-04-14 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Výzkum informačních technologií z hlediska bezpečnosti
number of pages	6 (xsd:int)
http://purl.org/ne...btex#hasPublisher	IEEE Computer Society
https://schema.org/isbn	978-1-4244-6610-8
http://localhost/t...ganizacniJednotka	26230

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