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  • In this paper it is demonstrated how two issues from the area of testing electronic components can be merged and solved by means of a genetic algorithm. The two issues are the ordering of test vectors and scan registers with the goal of reducing switching activity during test application and power consumption as a consequence of the ordering. The principles of developing an optimizing procedure with the aim of achieving a solution satisfying the required value of power consumption during power consumption are described here. A basic description of the methodology together with the functions needed to implement the procedures is provided. Experimental results are also discussed.
  • In this paper it is demonstrated how two issues from the area of testing electronic components can be merged and solved by means of a genetic algorithm. The two issues are the ordering of test vectors and scan registers with the goal of reducing switching activity during test application and power consumption as a consequence of the ordering. The principles of developing an optimizing procedure with the aim of achieving a solution satisfying the required value of power consumption during power consumption are described here. A basic description of the methodology together with the functions needed to implement the procedures is provided. Experimental results are also discussed. (en)
Title
  • The Use of Genetic Algorithm to Reduce Power Consumption during Test Application
  • The Use of Genetic Algorithm to Reduce Power Consumption during Test Application (en)
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  • The Use of Genetic Algorithm to Reduce Power Consumption during Test Application
  • The Use of Genetic Algorithm to Reduce Power Consumption during Test Application (en)
skos:notation
  • RIV/00216305:26230/10:PU89621!RIV11-GA0-26230___
http://linked.open...avai/riv/aktivita
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  • P(GA102/09/1668), S, Z(MSM0021630528)
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  • 294674
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  • RIV/00216305:26230/10:PU89621
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  • test application, power consumption, reduction, optimization, genetic algorithm, scan chain, scan register,&nbsp,test vector, reordering, benchmark, digital circuit (en)
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  • [967705EE356B]
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  • York
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  • Berlin
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  • Evolvable Systems: From Biology to Hardware
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  • Kotásek, Zdeněk
  • Strnadel, Josef
  • Škarvada, Jaroslav
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http://linked.open...n/vavai/riv/zamer
number of pages
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  • Springer-Verlag
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  • 978-3-642-15322-8
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  • 26230
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