About: Methodology for Design of Highly Dependable Systems in FPGA

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	In the paper, a survey of our research activities the goal of which is to develop a methodology allowing to design highly dependable system in FPGA is described. First, our experiences with partial dynamic reconfiguration in FPGA and application of partial reconfiguration as advanced solution for constructing of different types of fault tolerant architectures are described. Secondly, the main principles of methodology and first experiments with real fault tolerant designs based on partial dynamic reconfiguration implemented into Virtex5 and latest Virtex6 FPGAs are demonstrated.<br> In the paper, a survey of our research activities the goal of which is to develop a methodology allowing to design highly dependable system in FPGA is described. First, our experiences with partial dynamic reconfiguration in FPGA and application of partial reconfiguration as advanced solution for constructing of different types of fault tolerant architectures are described. Secondly, the main principles of methodology and first experiments with real fault tolerant designs based on partial dynamic reconfiguration implemented into Virtex5 and latest Virtex6 FPGAs are demonstrated.<br> (en)
Title	Methodology for Design of Highly Dependable Systems in FPGA Methodology for Design of Highly Dependable Systems in FPGA (en)
skos:prefLabel	Methodology for Design of Highly Dependable Systems in FPGA Methodology for Design of Highly Dependable Systems in FPGA (en)
skos:notation	RIV/00216305:26230/10:PU89555!RIV11-GA0-26230___
http://linked.open...avai/riv/aktivita	P S Z
http://linked.open...avai/riv/aktivity	P(GA102/09/1668), P(GD102/09/H042), S, Z(MSM0021630528)
http://linked.open...vai/riv/dodaniDat	2011
http://linked.open...aciTvurceVysledku	Straka, Martin Kotásek, Zdeněk Kaštil, Jan
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	270682
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/10:PU89555
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	system design, fault tolerance, architecture, reconfiguration, FPGA, soft error, methodology (en)
http://linked.open.../riv/klicoveSlovo	fault tolerance FPGA architecture - theory of architecture - empathy theory - style methodology system design reconfiguration soft error
http://linked.open...ontrolniKodProRIV	[F4CC417F9D80]
http://linked.open...v/mistoKonaniAkce	Stará Ľubovňa
http://linked.open...i/riv/mistoVydani	Košice
http://linked.open...i/riv/nazevZdroje	International Scientific Conference on Computer Science and Engineering
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...vavai/riv/projekt	SoC circuits reliability and availability improvement Mathematical and Engineering Approaches to Developing Reliable and Secure Concurrent and Distributed Computer Systems
http://linked.open...UplatneniVysledku	2010
http://linked.open...iv/tvurceVysledku	Kaštil, Jan Kotásek, Zdeněk Straka, Martin
http://linked.open...vavai/riv/typAkce	EUR - Evropská
http://linked.open.../riv/zahajeniAkce	2010-09-20 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Výzkum informačních technologií z hlediska bezpečnosti
number of pages	8 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Technická univerzita v Košiciach
https://schema.org/isbn	978-80-8086-164-3
http://localhost/t...ganizacniJednotka	26230

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