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  • The area of hardware/software co-design deals with the design of ASIPs(Application Specific Instruction-set Processors) because they often create the core of an embedded system. Embedded systems with ASIPs are designed for a given task and they have to fulfill several criteria, such as power consumption, chip size, etc. The success of the design phase is closely related to the existence of good design tools, i.e. tools for ASIP programming and simulation. The simulation itself is very important, because with it we can verify and validate an ASIP design. For this purpose, ASIPs are described using an architecture description language that allows generating the design tools in an automatic way. In this article, we focus on presenting the principles which are used in our fast cycle-accurate interpreted simulator. Beside the simulation speed, we also focus on equivalence assurance between an ASIP simulator and its hardware realization.
  • The area of hardware/software co-design deals with the design of ASIPs(Application Specific Instruction-set Processors) because they often create the core of an embedded system. Embedded systems with ASIPs are designed for a given task and they have to fulfill several criteria, such as power consumption, chip size, etc. The success of the design phase is closely related to the existence of good design tools, i.e. tools for ASIP programming and simulation. The simulation itself is very important, because with it we can verify and validate an ASIP design. For this purpose, ASIPs are described using an architecture description language that allows generating the design tools in an automatic way. In this article, we focus on presenting the principles which are used in our fast cycle-accurate interpreted simulator. Beside the simulation speed, we also focus on equivalence assurance between an ASIP simulator and its hardware realization. (en)
Title
  • Fast Cycle-Accurate Interpreted Simulation
  • Fast Cycle-Accurate Interpreted Simulation (en)
skos:prefLabel
  • Fast Cycle-Accurate Interpreted Simulation
  • Fast Cycle-Accurate Interpreted Simulation (en)
skos:notation
  • RIV/00216305:26230/09:PU86259!RIV12-MPO-26230___
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(FR-TI1/038), P(FT-TA3/128), P(GD102/09/H042), Z(MSM0021630503), Z(MSM0021630528)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 314693
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26230/09:PU86259
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • Hardware/software co-design, ASIP, Architecture description language, Cycle accurate interpreted simulation, Formal models. (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [29CEA04D33FF]
http://linked.open...v/mistoKonaniAkce
  • Austin, Texas
http://linked.open...i/riv/mistoVydani
  • Austin
http://linked.open...i/riv/nazevZdroje
  • Tenth International Workshop on Microprocessor Test and Verification: Common Challenges and Solutions
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Hruška, Tomáš
  • Husár, Adam
  • Masařík, Karel
  • Přikryl, Zdeněk
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • IEEE Computer Society Press
https://schema.org/isbn
  • 978-0-7695-4000-9
http://localhost/t...ganizacniJednotka
  • 26230
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