About: Reliability Models for Fault Tolerant Architectures Based on FPGA

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	In this presentation, a methodology of FTS design based on FPGA is<br>presented. The FT architectures are based both on duplex and TMR<br>systems to which fault detection capabilities are added, the use<br>of on-line checkers for this purpose is demonstrated. It is<br>described how reliability and availability parameters in TMR and<br>duplex structures with checkers can be increased. To demonstrate<br>this, analytical calculations based on Markov reliability model<br>are used. It is also shown how the availability parameters can be<br>affected by the operating environment into which the FTS is<br>implemented. Finally, the results of research and the comparison<br>of our approach with classical TMR and duplex architectures for<br>different failure rates are presented. In this presentation, a methodology of FTS design based on FPGA is<br>presented. The FT architectures are based both on duplex and TMR<br>systems to which fault detection capabilities are added, the use<br>of on-line checkers for this purpose is demonstrated. It is<br>described how reliability and availability parameters in TMR and<br>duplex structures with checkers can be increased. To demonstrate<br>this, analytical calculations based on Markov reliability model<br>are used. It is also shown how the availability parameters can be<br>affected by the operating environment into which the FTS is<br>implemented. Finally, the results of research and the comparison<br>of our approach with classical TMR and duplex architectures for<br>different failure rates are presented. (en)
Title	Reliability Models for Fault Tolerant Architectures Based on FPGA Reliability Models for Fault Tolerant Architectures Based on FPGA (en)
skos:prefLabel	Reliability Models for Fault Tolerant Architectures Based on FPGA Reliability Models for Fault Tolerant Architectures Based on FPGA (en)
skos:notation	RIV/00216305:26230/09:PU82705!RIV10-MSM-26230___
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(GD102/09/H042), Z(MSM0021630528)
http://linked.open...vai/riv/dodaniDat	2010
http://linked.open...aciTvurceVysledku	Straka, Martin Kotásek, Zdeněk
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	338844
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/09:PU82705
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	TMR, checker, fault tolerant system, reliability model, availability, FPGA (en)
http://linked.open.../riv/klicoveSlovo	FPGA availability fault tolerant system TMR checker reliability model
http://linked.open...ontrolniKodProRIV	[1640067CDDFB]
http://linked.open...v/mistoKonaniAkce	Znojmo
http://linked.open...i/riv/mistoVydani	Brno
http://linked.open...i/riv/nazevZdroje	5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...vavai/riv/projekt	Mathematical and Engineering Approaches to Developing Reliable and Secure Concurrent and Distributed Computer Systems
http://linked.open...UplatneniVysledku	2009
http://linked.open...iv/tvurceVysledku	Kotásek, Zdeněk Straka, Martin
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2009-11-13 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Výzkum informačních technologií z hlediska bezpečnosti
number of pages	1 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Masarykova univerzita. Fakulta informatiky
https://schema.org/isbn	978-80-87342-04-6
http://localhost/t...ganizacniJednotka	26230

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