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Description
  • Packet classification is an important operation for applications such as routers, firewalls or intrusion detection systems. Many algorithms and hardware architectures for packet classification have been created, but none of them can compete with the speed of TCAMs in the worst case. We propose new hardware-based algorithm for packet classification. The solution is based on problem decomposition and is aimed at the highest network speeds. A unique property of the algorithm is the constant time complexity in terms of external memory accesses. The algorithm performs exactly two external memory accesses to classify a packet. Using FPGA and one commodity SRAM chip, a throughput of 150 million packets per second can be achieved. This makes throughput of 100 Gbps for the shortest packets. Further performance scaling is possible with more or faster SRAM chips.
  • Packet classification is an important operation for applications such as routers, firewalls or intrusion detection systems. Many algorithms and hardware architectures for packet classification have been created, but none of them can compete with the speed of TCAMs in the worst case. We propose new hardware-based algorithm for packet classification. The solution is based on problem decomposition and is aimed at the highest network speeds. A unique property of the algorithm is the constant time complexity in terms of external memory accesses. The algorithm performs exactly two external memory accesses to classify a packet. Using FPGA and one commodity SRAM chip, a throughput of 150 million packets per second can be achieved. This makes throughput of 100 Gbps for the shortest packets. Further performance scaling is possible with more or faster SRAM chips. (en)
Title
  • Fast and scalable packet classification using perfect hash functions
  • Fast and scalable packet classification using perfect hash functions (en)
skos:prefLabel
  • Fast and scalable packet classification using perfect hash functions
  • Fast and scalable packet classification using perfect hash functions (en)
skos:notation
  • RIV/00216305:26230/09:PU82617!RIV10-MSM-26230___
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • Z(MSM0021630528), Z(MSM6383917201)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 314691
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26230/09:PU82617
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • classification, FPGA, perfect hash function (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [1AFFDD08F3B3]
http://linked.open...v/mistoKonaniAkce
  • Monterey, Californi
http://linked.open...i/riv/mistoVydani
  • New York
http://linked.open...i/riv/nazevZdroje
  • Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Kořenek, Jan
  • Puš, Viktor
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • Association for Computing Machinery
https://schema.org/isbn
  • 978-1-60558-410-2
http://localhost/t...ganizacniJednotka
  • 26230
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