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  • The EHWFILTER accelerator was developed in order to accelerate image filter evolution in hardware. It can automatically create a filter (e.g., to suppress shot noise) when noised image and uncorrupted original image are provided. The accelerator is implemented on the COMBO6X card equipped with Virtex II Pro 2VP50ff1517 FPGA. It consists of genetic unit, fitness unit and the so-called virtual reconfigurable circuit (VRC) which is utilized to evaluate candidate filters. Every image filter is considered as a digital circuit of nine 8-bit inputs and a single 8-bit output, which processes grayscale (8-bits/pixel) images. Training images are stored in external SRAM memories. The search algorithm is based on Cartesian Genetic Programming operating over 4x8 programmable elements, population size of 8 individuals, and 1 mutation/chromosome. This setting is default but can be changed. The accelerator is connected with PC using PCI bus. The system requires approx. 10 sec to produce a filter which is 44
  • The EHWFILTER accelerator was developed in order to accelerate image filter evolution in hardware. It can automatically create a filter (e.g., to suppress shot noise) when noised image and uncorrupted original image are provided. The accelerator is implemented on the COMBO6X card equipped with Virtex II Pro 2VP50ff1517 FPGA. It consists of genetic unit, fitness unit and the so-called virtual reconfigurable circuit (VRC) which is utilized to evaluate candidate filters. Every image filter is considered as a digital circuit of nine 8-bit inputs and a single 8-bit output, which processes grayscale (8-bits/pixel) images. Training images are stored in external SRAM memories. The search algorithm is based on Cartesian Genetic Programming operating over 4x8 programmable elements, population size of 8 individuals, and 1 mutation/chromosome. This setting is default but can be changed. The accelerator is connected with PC using PCI bus. The system requires approx. 10 sec to produce a filter which is 44 (en)
Title
  • Hardware Accelerator for Evolutionary Image Filters Design
  • Hardware Accelerator for Evolutionary Image Filters Design (en)
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  • Hardware Accelerator for Evolutionary Image Filters Design
  • Hardware Accelerator for Evolutionary Image Filters Design (en)
skos:notation
  • RIV/00216305:26230/09:PR24513!RIV10-MSM-26230___
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GA102/07/0850), Z(MSM0021630528)
http://linked.open...vai/riv/dodaniDat
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  • Cena závisí na počtu odebíraných kusů.
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  • 316850
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26230/09:PR24513
http://linked.open...terniIdentifikace
  • EHWFILTER
http://linked.open...riv/jazykVysledku
http://linked.open...vai/riv/kategorie
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  • accelerator, FPGA, Combo6X, evolutionary algorithm, image filter (en)
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http://linked.open...ontrolniKodProRIV
  • [B6D3FB839E2C]
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  • Ústav počítačových systémů, Fakulta informačních technologií VUT v Brně, Božetěchova 2, 612 66 Brno, http://www.fit.vutbr.cz/units/UPSY/
http://linked.open...in/vavai/riv/obor
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http://linked.open...vavai/riv/projekt
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  • Akcelerátor je implementován na kartě COMBO6X vybavené FPGA Virtex II Pro 2VP50ff1517 obsahující procesor PowerPC. Interně procesor pracuje na 300 MHz, podpůrná logika na 150 MHz. Ostatní komponenty akcelerátoru (virtuální rekonfigurovateln
http://linked.open...iv/tvurceVysledku
  • Sekanina, Lukáš
  • Vašíček, Zdeněk
http://linked.open...avai/riv/vlastnik
http://linked.open...itiJinymSubjektem
http://linked.open...n/vavai/riv/zamer
http://localhost/t...ganizacniJednotka
  • 26230
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