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  • In the paper, a survey of our research activities the goal of which is to develop a methodology allowing to design on-line checkers of digital components is described. First, our experiments with PSL language and FoCs tool are demonstrated. It is shown how PSL can be used to describe conditions to be checked by an on-line checker of a digital component. It is demonstrated that checkers generated from PSL description demand more sources than the unit under check which is seen as unacceptable result. The principles of our approach based on developing a formal language to describe the functions to be checked and a compiler which transforms the description into VHDL code are explained.
  • In the paper, a survey of our research activities the goal of which is to develop a methodology allowing to design on-line checkers of digital components is described. First, our experiments with PSL language and FoCs tool are demonstrated. It is shown how PSL can be used to describe conditions to be checked by an on-line checker of a digital component. It is demonstrated that checkers generated from PSL description demand more sources than the unit under check which is seen as unacceptable result. The principles of our approach based on developing a formal language to describe the functions to be checked and a compiler which transforms the description into VHDL code are explained. (en)
Title
  • The Design of Hardware Checkers for Verification and Diagnostic Purposes
  • The Design of Hardware Checkers for Verification and Diagnostic Purposes (en)
skos:prefLabel
  • The Design of Hardware Checkers for Verification and Diagnostic Purposes
  • The Design of Hardware Checkers for Verification and Diagnostic Purposes (en)
skos:notation
  • RIV/00216305:26230/08:PU76731!RIV10-MSM-26230___
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GD102/05/H050), Z(MSM0021630528)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 362683
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26230/08:PU76731
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • on-line checker, on-line testing, verification, PSL, FPGA, FoCs, ModelSim (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [4688E6533E94]
http://linked.open...v/mistoKonaniAkce
  • High Tatras - Stará Lesná
http://linked.open...i/riv/mistoVydani
  • High Tatras - Stará Lesná
http://linked.open...i/riv/nazevZdroje
  • CSE'2008 International Scientific Conference on Computer Science and Engineering
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Kotásek, Zdeněk
  • Straka, Martin
  • Winter, Jan
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • Technická univerzita v Košiciach
https://schema.org/isbn
  • 978-80-8086-092-9
http://localhost/t...ganizacniJednotka
  • 26230
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