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  • In the paper, the principles of a unit design which can be used for on-line communication protocol checking is presented. It is shown how the checker can be used to check the communication between IP cores implemented in FPGA. The checker watches the communication and detects such states which do not satisfy protocol definitions. If such a situation appears, it is indicated that hardware implementation does not work properly. The communication must be precisely defined - for this purpose, a formal approach was developed which allows to describe ambiguously the conditions which must be satisfied during the communication. From the description, the checker description in VHDL is generated (a compiler was developed for this purpose) and implemented into FPGA. The methodology was verified on LocalLink communication protocol developed by Xilinx, Virtex 2 Pro and Virtex4 FPGAs were used for the implementation.
  • In the paper, the principles of a unit design which can be used for on-line communication protocol checking is presented. It is shown how the checker can be used to check the communication between IP cores implemented in FPGA. The checker watches the communication and detects such states which do not satisfy protocol definitions. If such a situation appears, it is indicated that hardware implementation does not work properly. The communication must be precisely defined - for this purpose, a formal approach was developed which allows to describe ambiguously the conditions which must be satisfied during the communication. From the description, the checker description in VHDL is generated (a compiler was developed for this purpose) and implemented into FPGA. The methodology was verified on LocalLink communication protocol developed by Xilinx, Virtex 2 Pro and Virtex4 FPGAs were used for the implementation. (en)
Title
  • Checkers Design for Communication Protocols Based on FPGAs
  • Checkers Design for Communication Protocols Based on FPGAs (en)
skos:prefLabel
  • Checkers Design for Communication Protocols Based on FPGAs
  • Checkers Design for Communication Protocols Based on FPGAs (en)
skos:notation
  • RIV/00216305:26230/08:PU76697!RIV10-MSM-26230___
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GD102/05/H050), Z(MSM0021630528)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 359694
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26230/08:PU76697
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • on-line checker, communication protocol, FPGA, LocalLink, VHDL (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [60D5AC9AC276]
http://linked.open...v/mistoKonaniAkce
  • FEKT VUT v Brně
http://linked.open...i/riv/mistoVydani
  • Brno
http://linked.open...i/riv/nazevZdroje
  • Proceedings of the 14th Conference STUDENT EEICT 2008 Volume 4
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Straka, Martin
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • Vysoké učení technické v Brně. Fakulta informačních technologií
https://schema.org/isbn
  • 978-80-214-3617-6
http://localhost/t...ganizacniJednotka
  • 26230
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