| Attributes | Values |
|---|
| rdf:type
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| Description
| - In the paper, the principles of a unit design which can be used for on-line communication protocol checking is presented. It is shown how the checker can be used to check the communication between IP cores implemented in FPGA. The communication must be precisely defined - for this purpose, a formal approach was developed which allows to describe ambiguously the conditions which must be satisfied during the communication. From the description, the checker description in VHDL is generated (a compiler was developed for this purpose) and implemented into FPGA. The checker watches the communication and detects such states which do not satisfy protocol definitions. If such a situation appears, it is indicated that hardware implementation does not work properly. The methodology was verified on LocalLink communication protocol developed by Xilinx, Virtex 2 Pro FPGA was used for the implementation. Future research will be directed towards the development of fault tolerant systems<br>design methodology in which
- In the paper, the principles of a unit design which can be used for on-line communication protocol checking is presented. It is shown how the checker can be used to check the communication between IP cores implemented in FPGA. The communication must be precisely defined - for this purpose, a formal approach was developed which allows to describe ambiguously the conditions which must be satisfied during the communication. From the description, the checker description in VHDL is generated (a compiler was developed for this purpose) and implemented into FPGA. The checker watches the communication and detects such states which do not satisfy protocol definitions. If such a situation appears, it is indicated that hardware implementation does not work properly. The methodology was verified on LocalLink communication protocol developed by Xilinx, Virtex 2 Pro FPGA was used for the implementation. Future research will be directed towards the development of fault tolerant systems<br>design methodology in which (en)
- In the paper, the principles of a unit design which can be used for on-line communication protocol checking is presented. It is shown how the checker can be used to check the communication between IP cores implemented in FPGA. The communication must be precisely defined - for this purpose, a formal approach was developed which allows to describe ambiguously the conditions which must be satisfied during the communication. From the description, the checker description in VHDL is generated (a compiler was developed for this purpose) and implemented into FPGA. The checker watches the communication and detects such states which do not satisfy protocol definitions. If such a situation appears, it is indicated that hardware implementation does not work properly. The methodology was verified on LocalLink communication protocol developed by Xilinx, Virtex 2 Pro FPGA was used for the implementation. Future research will be directed towards the development of fault tolerant systems<br>design methodology in which (cs)
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| Title
| - Checker for Communication Protocol between IP Cores Based on FPGA
- Checker for Communication Protocol between IP Cores Based on FPGA (en)
- Checker for Communication Protocol between IP Cores Based on FPGA (cs)
|
| skos:prefLabel
| - Checker for Communication Protocol between IP Cores Based on FPGA
- Checker for Communication Protocol between IP Cores Based on FPGA (en)
- Checker for Communication Protocol between IP Cores Based on FPGA (cs)
|
| skos:notation
| - RIV/00216305:26230/07:PU70895!RIV08-MSM-26230___
|
| http://linked.open.../vavai/riv/strany
| |
| http://linked.open...avai/riv/aktivita
| |
| http://linked.open...avai/riv/aktivity
| - P(GD102/05/H050), Z(MSM0021630528)
|
| http://linked.open...vai/riv/dodaniDat
| |
| http://linked.open...aciTvurceVysledku
| |
| http://linked.open.../riv/druhVysledku
| |
| http://linked.open...iv/duvernostUdaju
| |
| http://linked.open...titaPredkladatele
| |
| http://linked.open...dnocenehoVysledku
| |
| http://linked.open...ai/riv/idVysledku
| - RIV/00216305:26230/07:PU70895
|
| http://linked.open...riv/jazykVysledku
| |
| http://linked.open.../riv/klicovaSlova
| - core generator, VHDL, FPGA, grammar, checker, IP-core (en)
|
| http://linked.open.../riv/klicoveSlovo
| |
| http://linked.open...ontrolniKodProRIV
| |
| http://linked.open...v/mistoKonaniAkce
| |
| http://linked.open...i/riv/mistoVydani
| |
| http://linked.open...i/riv/nazevZdroje
| - 3rd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
|
| http://linked.open...in/vavai/riv/obor
| |
| http://linked.open...ichTvurcuVysledku
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| http://linked.open...cetTvurcuVysledku
| |
| http://linked.open...vavai/riv/projekt
| |
| http://linked.open...UplatneniVysledku
| |
| http://linked.open...iv/tvurceVysledku
| - Kotásek, Zdeněk
- Straka, Martin
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| http://linked.open...vavai/riv/typAkce
| |
| http://linked.open.../riv/zahajeniAkce
| |
| http://linked.open...n/vavai/riv/zamer
| |
| number of pages
| |
| http://purl.org/ne...btex#hasPublisher
| - Masarykova univerzita. Fakulta informatiky
|
| https://schema.org/isbn
| |
| http://localhost/t...ganizacniJednotka
| |
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