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Description
  • Our team performs some research activities at the field of testability in past years. These activities results in testability analysis, testability verification, test scheduling and test controller synthesis methodologies. All methodologies are described formally using language of mathematics and theoretical computer science and are based on a formal model of the RT level digital circuit. These tasks can be performed by the iFCoRT system (I path Based, Formally Described and Proved Concept of RTL Digital Circuits Testability). This paper describes how the system can be used during design-for-testability process - a design flow of a testable RT level digital circuit.
  • Our team performs some research activities at the field of testability in past years. These activities results in testability analysis, testability verification, test scheduling and test controller synthesis methodologies. All methodologies are described formally using language of mathematics and theoretical computer science and are based on a formal model of the RT level digital circuit. These tasks can be performed by the iFCoRT system (I path Based, Formally Described and Proved Concept of RTL Digital Circuits Testability). This paper describes how the system can be used during design-for-testability process - a design flow of a testable RT level digital circuit. (en)
  • Výzkumná skupina diagnostiky na UPSY FIT VUT v Brně dosáhla v posledních letech některých zajímavých výsledků. Její výzkumné aktivity pokrývají analýzu testovatelnosti, verifikaci testovatelnosti, plánování testu a syntézu řadiče testu. Všechny metodiky jsou důsledně popsány formálně jazykem matematiky a teoretické informatiky a jsou založeny na formálním modelu číslicového obvodu na úrovni RT. Všechny popsané aktivity jsou nyní sjednoceny do systému iFCoRT (I path Based, Formally Described and Proved Concept of RTL Digital Circuits Testability). Tento článek popisuje, jak může být systém iFCoRT využit při návrhu pro snadnou testovatelnost. (cs)
Title
  • DFT Flow for RT Level Digital Circuits Using iFCoRT System
  • Návrhový tok návrhu pro snadnou testovatelnost číslicových systémů na úrovni RT s využitím systému iFCoRT (cs)
  • DFT Flow for RT Level Digital Circuits Using iFCoRT System (en)
skos:prefLabel
  • DFT Flow for RT Level Digital Circuits Using iFCoRT System
  • Návrhový tok návrhu pro snadnou testovatelnost číslicových systémů na úrovni RT s využitím systému iFCoRT (cs)
  • DFT Flow for RT Level Digital Circuits Using iFCoRT System (en)
skos:notation
  • RIV/00216305:26230/06:PU66974!RIV07-GA0-26230___
http://linked.open.../vavai/riv/strany
  • 292-297
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GA102/04/0737)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
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  • 471346
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  • RIV/00216305:26230/06:PU66974
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  • Testability Analysis, Testability Verification, Design-for-Testability (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [A1EFCD44313B]
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  • Herľany
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  • Košice
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  • Proceedings of the Seventh International Scientific Conference Electronic Computers and Informatics ECI 2006
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  • Růžička, Richard
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number of pages
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  • Neuveden
https://schema.org/isbn
  • 80-8073-598-0
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  • 26230
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