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Description
  • Příspěvek se zabývá plánováním testu pro číslicové systémy. Je prezentován přístup založený na využítí C/E Petriho sítí. Model je využit pro nalezení strukturních konfliktů a deadloků, které se mohou vyskytnout při plánování testu. Číslicový systém je analyzován na úrovni RTL. Výsledky metody mohou být také využity při rozdělování číslicového systému na jednotlivé logické bloky. Znalost strukturních závislostí lze potom s výhodou použít při plánování testu jednotlivých logických bloků. (cs)
  • The paper deals with test scheduling for digital systems. Approach with C/E Petri nets is presented and formal model of digital system under test is introduced. Main purpose of this model is identification of structural conflicts and dead locks that may occur during test application phase. The digital system is analyzed on register transfer (RT) level. The obtained results can be used for digital system design partitioning. In this step individual blocks of logic are identified. Finally concurrent test for non-conflicting blocks of logic is scheduled. The advantage of this approach is, that with partitioned circuit, it is possible to view digital circuit design as system on chip (SOC) design and use existing test scheduling methods for SOC.
  • The paper deals with test scheduling for digital systems. Approach with C/E Petri nets is presented and formal model of digital system under test is introduced. Main purpose of this model is identification of structural conflicts and dead locks that may occur during test application phase. The digital system is analyzed on register transfer (RT) level. The obtained results can be used for digital system design partitioning. In this step individual blocks of logic are identified. Finally concurrent test for non-conflicting blocks of logic is scheduled. The advantage of this approach is, that with partitioned circuit, it is possible to view digital circuit design as system on chip (SOC) design and use existing test scheduling methods for SOC. (en)
Title
  • Using Petri Nets for RT Level Digital Systems Test Scheduling
  • Using Petri Nets for RT Level Digital Systems Test Scheduling (en)
  • Využití Petriho sítí pro plánování testu číslicových systémů na úrovni RTL (cs)
skos:prefLabel
  • Using Petri Nets for RT Level Digital Systems Test Scheduling
  • Using Petri Nets for RT Level Digital Systems Test Scheduling (en)
  • Využití Petriho sítí pro plánování testu číslicových systémů na úrovni RTL (cs)
skos:notation
  • RIV/00216305:26230/06:PU66877!RIV07-GA0-26230___
http://linked.open.../vavai/riv/strany
  • 79-86
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GA102/04/0737)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 505391
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26230/06:PU66877
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • Digital circuit, C/E Petri Net, test scheduling, I-paths, structural conflicts (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [9A854ECA9252]
http://linked.open...v/mistoKonaniAkce
  • Přerov
http://linked.open...i/riv/mistoVydani
  • Ostrava
http://linked.open...i/riv/nazevZdroje
  • Proceedings of 1st International Workshop on Formal Models (WFM'06)
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Růžička, Richard
  • Škarvada, Jaroslav
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
number of pages
http://purl.org/ne...btex#hasPublisher
  • Neuveden
https://schema.org/isbn
  • 80-86840-20-4
http://localhost/t...ganizacniJednotka
  • 26230
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