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  • This paper discusses some problems with test scheduling optimization of register transfer level (RTL) digital circuit design. The Petri net model, previously proposed for testability verification purposes is now used as a base of C/E system which models test application process. To schedule application of test patterns to elements of a circuit under test, possibility of concurrency must be considered firstly. Parallelism during test application process can significantly reduce time of testing. Another aadvantage of the approach is that all methods are described formally and are proved.
  • This paper discusses some problems with test scheduling optimization of register transfer level (RTL) digital circuit design. The Petri net model, previously proposed for testability verification purposes is now used as a base of C/E system which models test application process. To schedule application of test patterns to elements of a circuit under test, possibility of concurrency must be considered firstly. Parallelism during test application process can significantly reduce time of testing. Another aadvantage of the approach is that all methods are described formally and are proved. (en)
  • Článek řeší některé problémy optimalizace plánování testu číslicového obvodu na úrovni RT. Pro tyto účely je nyní použit model založený na Petriho sítích, který byl již dříve navržen pro účely verifikace testovatelnosti. Model je základem C/E systému, modelujícího proces aplikace testu. Pro optimalizaci rozvržení testu jsou významné zejména možnosti paralelní aplikace testu na více prvků současně. Užití paralelismu při aplikaci testu může výrazně snížit dobu testu. Výhodou popsaného přístupu je čisstě formální popis a ověření správnosti formou matematických důkazů. (cs)
Title
  • On the Petri Net Based Test Scheduling
  • K plánování testu založeném na Petriho sítích (cs)
  • On the Petri Net Based Test Scheduling (en)
skos:prefLabel
  • On the Petri Net Based Test Scheduling
  • K plánování testu založeném na Petriho sítích (cs)
  • On the Petri Net Based Test Scheduling (en)
skos:notation
  • RIV/00216305:26230/05:PU56454!RIV06-GA0-26230___
http://linked.open.../vavai/riv/strany
  • 18-19
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GA102/04/0737), P(GP102/03/P176)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 534494
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26230/05:PU56454
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • RTL digital circuit testability, test scheduling optimization (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [9D17CAC5081B]
http://linked.open...v/mistoKonaniAkce
  • Faculdade de Engenharia da Universidade do Porto
http://linked.open...i/riv/mistoVydani
  • Linz
http://linked.open...i/riv/nazevZdroje
  • Proceedings of the Work in Progress Session at Euromicro SEAA/DSD 2005
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Růžička, Richard
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
number of pages
http://purl.org/ne...btex#hasPublisher
  • Johannes Kepler University Linz
https://schema.org/isbn
  • 3-902457-09-0
http://localhost/t...ganizacniJednotka
  • 26230
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