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rdf:type
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Description
| - Článek popisuje kompletní obvodovou realizaci vyvíjející se kombinační jednotky pro FPGA. Navržená jednotka sestávající z virtuálního rekonfigurovatelného obvodu a evolučního algoritmu byla popsána ve VHDL nezávisle na cílové platformě, tj. jako soft IPcore, a implementována na kartě Combo6. Jednotka je schopna automaticky vyevolvovat realizaci požadované kombinační funkce pouze na základě interakce s prostředím. (cs)
- A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evolutionary algorithm was described in VHDL independently of a target platform, i.e. as a soft IP core, and realized in the COMBO6 card. In many cases the unit is able to evolve (i.e. to design) the required function automatically and autonomously, in a few seconds, only on the basis of interactions with an environment. A numberr of circuits were successfully evolved directly in the FPGA, in particular, 3-bit multipliers, adders, multiplexers and parity encoders. The evolvable unit was also tested in a simulated dynamic environment and used to design various circuits specifiedby randomly generated truth tables. <br>
- A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evolutionary algorithm was described in VHDL independently of a target platform, i.e. as a soft IP core, and realized in the COMBO6 card. In many cases the unit is able to evolve (i.e. to design) the required function automatically and autonomously, in a few seconds, only on the basis of interactions with an environment. A numberr of circuits were successfully evolved directly in the FPGA, in particular, 3-bit multipliers, adders, multiplexers and parity encoders. The evolvable unit was also tested in a simulated dynamic environment and used to design various circuits specifiedby randomly generated truth tables. <br> (en)
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Title
| - An Evolvable Combinational Unit for FPGAs
- An Evolvable Combinational Unit for FPGAs (en)
- Vyvíjející se kombinační jednotka pro FPGA (cs)
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skos:prefLabel
| - An Evolvable Combinational Unit for FPGAs
- An Evolvable Combinational Unit for FPGAs (en)
- Vyvíjející se kombinační jednotka pro FPGA (cs)
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skos:notation
| - RIV/00216305:26230/04:PU50053!RIV/2005/GA0/262305/N
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http://linked.open.../vavai/riv/strany
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http://linked.open...avai/riv/aktivita
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http://linked.open...avai/riv/aktivity
| - P(GA102/04/0737), P(GP102/03/P004)
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http://linked.open...iv/cisloPeriodika
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http://linked.open...vai/riv/dodaniDat
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http://linked.open...aciTvurceVysledku
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http://linked.open.../riv/druhVysledku
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http://linked.open...iv/duvernostUdaju
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http://linked.open...titaPredkladatele
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http://linked.open...dnocenehoVysledku
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http://linked.open...ai/riv/idVysledku
| - RIV/00216305:26230/04:PU50053
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http://linked.open...riv/jazykVysledku
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http://linked.open.../riv/klicovaSlova
| - combinational circuit, evolutionary design, evolvable hardware, field programmable gate array<br> (en)
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http://linked.open.../riv/klicoveSlovo
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http://linked.open...odStatuVydavatele
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http://linked.open...ontrolniKodProRIV
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http://linked.open...i/riv/nazevZdroje
| - Computing and Informatics
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http://linked.open...in/vavai/riv/obor
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http://linked.open...ichTvurcuVysledku
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http://linked.open...cetTvurcuVysledku
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http://linked.open...vavai/riv/projekt
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http://linked.open...UplatneniVysledku
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http://linked.open...v/svazekPeriodika
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http://linked.open...iv/tvurceVysledku
| - Sekanina, Lukáš
- Friedl, Štěpán
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issn
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number of pages
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http://localhost/t...ganizacniJednotka
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