About: Testing PCBs Based on Boundary Scan

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	The paper describes a practical approach to testing PCBs with Xilinx FPGAs. The approach is based on a PCB netlist analysis, which is revealing the existing connections on the PCB through the Boundary Scan chain and comparing the two results. It is also supposed that the developed software tools will be used for debugging PCBs with Xilinx FPGAs. The goal of the research activities is to develop an easy to use an efficient and user- friendly software tools. The paper describes a practical approach to testing PCBs with Xilinx FPGAs. The approach is based on a PCB netlist analysis, which is revealing the existing connections on the PCB through the Boundary Scan chain and comparing the two results. It is also supposed that the developed software tools will be used for debugging PCBs with Xilinx FPGAs. The goal of the research activities is to develop an easy to use an efficient and user- friendly software tools. (en)
Title	Testing PCBs Based on Boundary Scan Testing PCBs Based on Boundary Scan (en)
skos:prefLabel	Testing PCBs Based on Boundary Scan Testing PCBs Based on Boundary Scan (en)
skos:notation	RIV/00216305:26230/03:PU42562!RIV/2004/GA0/262304/N
http://linked.open.../vavai/riv/strany	119-122
http://linked.open...avai/riv/aktivita	P
http://linked.open...avai/riv/aktivity	P(GA102/01/1531)
http://linked.open...vai/riv/dodaniDat	2004
http://linked.open...aciTvurceVysledku	Kotásek, Zdeněk Tupec, Pavel Urbiš, Hynek
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	630739
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/03:PU42562
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Boundary Scan, PCB, FPGA (en)
http://linked.open.../riv/klicoveSlovo	PCB FPGA Boundary Scan
http://linked.open...ontrolniKodProRIV	[7973729282E1]
http://linked.open...v/mistoKonaniAkce	Vysoké Tatry
http://linked.open...i/riv/mistoVydani	Košice
http://linked.open...i/riv/nazevZdroje	Proceedings of International Carpathian Control Conference
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...ocetUcastnikuAkce	0 (xsd:int)
http://linked.open...nichUcastnikuAkce	0 (xsd:int)
http://linked.open...vavai/riv/projekt	Formal approaches in digital circuit diagnostics - testable design verification
http://linked.open...UplatneniVysledku	2003
http://linked.open...iv/tvurceVysledku	Kotásek, Zdeněk Tupec, Pavel Urbiš, Hynek
http://linked.open...vavai/riv/typAkce	EUR - Evropská
http://linked.open.../riv/zahajeniAkce	2003-05-26 (xsd:date)
number of pages	4 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Technická univerzita v Košiciach
https://schema.org/isbn	80-7099-509-2
http://localhost/t...ganizacniJednotka	26230

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