About: A Design Space Exploration Scheme for High-Level Synthesis Systems

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	This paper describes a design exploration methodology that includes scheduling, module selection and clock cycle determination. The underlying methodology is constructed from one preliminary step and three main phases that allow improving every phase independently from the others without affecting their results, as well as it allows incorporation of the proposed techniques in any high-level synthesis system. The method starts by resource-constrained scheduling algorithm, which incorporates a local explooration mechanism to explore the design points so that each change in the resource set is considered as one point in the design space, which need to be further explored during the module selection step. Then during the module selection phase, the methodology systematically explores several combinations of hardware resource configurations (modules configuration set) that are satisfying time constraints and reports the optimal set with a minimum design area to the designer. Finally, clock cycle exploratio This paper describes a design exploration methodology that includes scheduling, module selection and clock cycle determination. The underlying methodology is constructed from one preliminary step and three main phases that allow improving every phase independently from the others without affecting their results, as well as it allows incorporation of the proposed techniques in any high-level synthesis system. The method starts by resource-constrained scheduling algorithm, which incorporates a local explooration mechanism to explore the design points so that each change in the resource set is considered as one point in the design space, which need to be further explored during the module selection step. Then during the module selection phase, the methodology systematically explores several combinations of hardware resource configurations (modules configuration set) that are satisfying time constraints and reports the optimal set with a minimum design area to the designer. Finally, clock cycle exploratio (en)
Title	A Design Space Exploration Scheme for High-Level Synthesis Systems A Design Space Exploration Scheme for High-Level Synthesis Systems (en)
skos:prefLabel	A Design Space Exploration Scheme for High-Level Synthesis Systems A Design Space Exploration Scheme for High-Level Synthesis Systems (en)
skos:notation	RIV/00216305:26230/02:PU36194!RIV/2003/GA0/262303/N
http://linked.open.../vavai/riv/strany	305-312
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(GA102/01/1531), Z(MSM 262200012)
http://linked.open...vai/riv/dodaniDat	2003
http://linked.open...aciTvurceVysledku	Drábek, Vladimír
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	636984
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/02:PU36194
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	High-Level Synthesis, scheduling, Design space exploration (en)
http://linked.open.../riv/klicoveSlovo	scheduling Design space exploration High-Level Synthesis
http://linked.open...ontrolniKodProRIV	[0B94110820B2]
http://linked.open...v/mistoKonaniAkce	Rožnov pod Radhoštěm
http://linked.open...i/riv/mistoVydani	Ostrava
http://linked.open...i/riv/nazevZdroje	Proceedings of 36th International Conference MOSIS '02 Modelling and Simulation of Systems
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	1 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...ocetUcastnikuAkce	0 (xsd:int)
http://linked.open...nichUcastnikuAkce	0 (xsd:int)
http://linked.open...vavai/riv/projekt	Formal approaches in digital circuit diagnostics - testable design verification
http://linked.open...UplatneniVysledku	2002
http://linked.open...iv/tvurceVysledku	Drábek, Vladimír Sllame M., Azeddien
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2002-04-22 (xsd:date)
http://linked.open...n/vavai/riv/zamer	http://linked.opendata.cz/resource/domain/vavai/zamer/MSM%20262200012
number of pages	8 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Neuveden
https://schema.org/isbn	80-85988-71-2
http://localhost/t...ganizacniJednotka	26230

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