About: Boundary Scan of PCBs with Xilinx FPGAs

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	The paper describes the research activities the goal of which is to develop simple software tools for applying test to printed circuit boards based on Xilinx XC4000 through Boundary Scan (BS) registers and deriving the set of test vectors on the basis of the EDIF data analysis. The possible configurations of scan chains are discussed. The principles of controlling the test application are discussed in detail. The paper describes the research activities the goal of which is to develop simple software tools for applying test to printed circuit boards based on Xilinx XC4000 through Boundary Scan (BS) registers and deriving the set of test vectors on the basis of the EDIF data analysis. The possible configurations of scan chains are discussed. The principles of controlling the test application are discussed in detail. (en)
Title	Boundary Scan of PCBs with Xilinx FPGAs Boundary Scan of PCBs with Xilinx FPGAs (en)
skos:prefLabel	Boundary Scan of PCBs with Xilinx FPGAs Boundary Scan of PCBs with Xilinx FPGAs (en)
skos:notation	RIV/00216305:26220/99:43801003!RIV/2000/MSM/262200
http://linked.open.../vavai/riv/strany	70
http://linked.open...avai/riv/aktivita	P
http://linked.open...avai/riv/aktivity	P(GA102/98/1463)
http://linked.open...vai/riv/dodaniDat	2000
http://linked.open...aciTvurceVysledku	Kotásek, Zdeněk Zbořil, František
http://linked.open.../riv/druhVysledku	C - Kapitola v knize
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta elektrotechniky a komunikačních technologií
http://linked.open...dnocenehoVysledku	736063
http://linked.open...ai/riv/idVysledku	RIV/00216305:26220/99:43801003
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Design for testability; Boundary Scan; PCBs Testing; Xilinx FPGAs (en)
http://linked.open.../riv/klicoveSlovo	Design for testability Boundary Scan PCBs Testing Xilinx FPGAs
http://linked.open...ontrolniKodProRIV	[057A8C06F580]
http://linked.open...i/riv/mistoVydani	Herlany, Slovenská Republika
http://linked.open...i/riv/nazevZdroje	Sborník konference ECI98
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...vavai/riv/projekt	Methodology and tools for digital circuits testability analysis
http://linked.open...UplatneniVysledku	1999
http://linked.open...iv/tvurceVysledku	Kotásek, Zdeněk Zbořil, František
number of pages	5 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Academic Press, Kosice
https://schema.org/isbn	80-88786-94-0
http://localhost/t...ganizacniJednotka	26220

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