About: Control Speed of DC Motor Using PWM FPGA

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	This article deals with the design pulse width modulation using field programmable gate arrays in order to control the speed of small DC motor, We need to counter, data and comparator that generate the signal of PWM. We can gate on the output of pwm that drive the speed of motor by use the peripherals inside the board FPGA. This article explains how we can gate on the data of components (counter, data, comparator) by use the language VHDL. The program ISE13 by XILINX supports this language.We need too to clock which we can obtain inside the board FPGA. But the frequency of this clock is very high and we have to divide this value by use the clock manager and the counter. When we finish the write of program, we can see the signal of PWM by oscilloscope. We control the signal by change the PWM frequency using switches that exist on the board. This article deals with the design pulse width modulation using field programmable gate arrays in order to control the speed of small DC motor, We need to counter, data and comparator that generate the signal of PWM. We can gate on the output of pwm that drive the speed of motor by use the peripherals inside the board FPGA. This article explains how we can gate on the data of components (counter, data, comparator) by use the language VHDL. The program ISE13 by XILINX supports this language.We need too to clock which we can obtain inside the board FPGA. But the frequency of this clock is very high and we have to divide this value by use the clock manager and the counter. When we finish the write of program, we can see the signal of PWM by oscilloscope. We control the signal by change the PWM frequency using switches that exist on the board. (en)
Title	Control Speed of DC Motor Using PWM FPGA Control Speed of DC Motor Using PWM FPGA (en)
skos:prefLabel	Control Speed of DC Motor Using PWM FPGA Control Speed of DC Motor Using PWM FPGA (en)
skos:notation	RIV/00216305:26220/12:PU98560!RIV14-MSM-26220___
http://linked.open...avai/riv/aktivita	S
http://linked.open...avai/riv/aktivity	S
http://linked.open...vai/riv/dodaniDat	2014
http://linked.open...aciTvurceVysledku	Nouman, Ziad
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta elektrotechniky a komunikačních technologií
http://linked.open...dnocenehoVysledku	128708
http://linked.open...ai/riv/idVysledku	RIV/00216305:26220/12:PU98560
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	DC MOTOR, FPGA, ISE, PWM, VHDL (en)
http://linked.open.../riv/klicoveSlovo	VHDL ISE PWM FPGA DC MOTOR
http://linked.open...ontrolniKodProRIV	[30E74CE4976D]
http://linked.open...v/mistoKonaniAkce	Brno
http://linked.open...i/riv/mistoVydani	Brno
http://linked.open...i/riv/nazevZdroje	In Proccedings of the 13th International Scientific Conference Electric Power Engineering 2012
http://linked.open...in/vavai/riv/obor	JA
http://linked.open...ichTvurcuVysledku	1 (xsd:int)
http://linked.open...cetTvurcuVysledku	1 (xsd:int)
http://linked.open...UplatneniVysledku	2012
http://linked.open...iv/tvurceVysledku	Nouman, Ziad
http://linked.open...vavai/riv/typAkce	EUR - Evropská
http://linked.open.../riv/zahajeniAkce	2012-05-23 (xsd:date)
number of pages	5 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Vysoké učení technické v Brně
https://schema.org/isbn	978-80-214-4514-7
http://localhost/t...ganizacniJednotka	26220

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