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  • This paper describes the design of a 10-b fully differential pipelined analog-to-digital converter (ADC). The pipelined ADC has been designed using the switched-opamp technique without calibration in a 0.7 um CMOS process for sensor applications. Low power consumption is one of the most important issues. An operational amplifier (opamp) sharing technique was used to decrease the power usage.
  • This paper describes the design of a 10-b fully differential pipelined analog-to-digital converter (ADC). The pipelined ADC has been designed using the switched-opamp technique without calibration in a 0.7 um CMOS process for sensor applications. Low power consumption is one of the most important issues. An operational amplifier (opamp) sharing technique was used to decrease the power usage. (en)
Title
  • Design of a 10-b Pipelined ADC without calibration
  • Design of a 10-b Pipelined ADC without calibration (en)
skos:prefLabel
  • Design of a 10-b Pipelined ADC without calibration
  • Design of a 10-b Pipelined ADC without calibration (en)
skos:notation
  • RIV/00216305:26220/11:PU95441!RIV12-MSM-26220___
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  • P(GAP102/11/1379), S
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  • 193542
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  • RIV/00216305:26220/11:PU95441
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  • Pipelined ADC, MDAC, SC technique, operational amplifier, comparator, opamp sharing technique (en)
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  • [184A146456B3]
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  • Puerto De La Cruz, Tenerife
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  • Tenerife, Španělsko
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  • Recent Researches in Circuits, Systems, Communications & Computers
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  • Háze, Jiří
  • Kledrowetz, Vilém
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number of pages
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  • WSEAS Press
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  • 978-1-61804-056-5
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  • 26220
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