About: VHDL Procedure for Combinational Divider

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	In the paper, a synthesizable combinational integer number divider VHDL model is described that is suitable for implementation in the FPGA devices. The algorithm the divider is based on is briefly introduced. Along the model, testbench for its functional verification is presented. Results of implementation in Xilinx Spartan-3 and Spartan-6 devices - amount of FPGA resources used and maximum delay, are given in tables. In the paper, a synthesizable combinational integer number divider VHDL model is described that is suitable for implementation in the FPGA devices. The algorithm the divider is based on is briefly introduced. Along the model, testbench for its functional verification is presented. Results of implementation in Xilinx Spartan-3 and Spartan-6 devices - amount of FPGA resources used and maximum delay, are given in tables. (en)
Title	VHDL Procedure for Combinational Divider VHDL Procedure for Combinational Divider (en)
skos:prefLabel	VHDL Procedure for Combinational Divider VHDL Procedure for Combinational Divider (en)
skos:notation	RIV/00216305:26220/11:PU94781!RIV13-MSM-26220___
http://linked.open...avai/riv/aktivita	P S Z
http://linked.open...avai/riv/aktivity	P(EE2.3.20.0007), P(GPP102/10/P513), S, Z(MSM0021630513)
http://linked.open...vai/riv/dodaniDat	2013
http://linked.open...aciTvurceVysledku	Kolouch, Jaromír Fedra, Zbyněk
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta elektrotechniky a komunikačních technologií
http://linked.open...dnocenehoVysledku	238326
http://linked.open...ai/riv/idVysledku	RIV/00216305:26220/11:PU94781
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	divider, FPGA, implementation, procedure, static timing analysis, VHDL (en)
http://linked.open.../riv/klicoveSlovo	VHDL procedure FPGA implementation divider static timing analysis
http://linked.open...ontrolniKodProRIV	[EED537D3556B]
http://linked.open...v/mistoKonaniAkce	Budapest
http://linked.open...i/riv/mistoVydani	Neuveden
http://linked.open...i/riv/nazevZdroje	34th International Conference on Telecommunications and Signal Processing, TSP 2011
http://linked.open...in/vavai/riv/obor	JA
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...vavai/riv/projekt	Wireless communication teams Communication systems combining OFDM and CDMA and their PAPR
http://linked.open...UplatneniVysledku	2011
http://linked.open...iv/tvurceVysledku	Kolouch, Jaromír Fedra, Zbyněk
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2011-08-18 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Advanced Electronic Communication Systems and Technologies (ELCOM)
number of pages	3 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Neuveden
https://schema.org/isbn	978-1-4577-1761-1
http://localhost/t...ganizacniJednotka	26220

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