About: Introduction to the New Packet Triggered Architecture for Pipelined and Parallel Data Processing

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About: Introduction to the New Packet Triggered Architecture for Pipelined and Parallel Data Processing Goto Sponge NotDistinct Permalink

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	This paper describes a novel Packet Triggered Architecture (PTA). This architecture takes advantage of programmable pipeline and parallel processing, which lead to MIMD (Multiple Instruction Multiple Data) architecture. The PTA is composed of two main blocks. The first block is constituted from Functional Units (FUs) and their interconnection network. The instructions in the PTA are composed of instruction packets. Every packet encapsulates a data and route across internal NoC (Network on Chip) to which enables dynamic data flow scheduling. This approach brings a new way of programming, because the programming is done by specifying FUs addresses and functions ports. Using of such a design allows create target hardware like a software application. The main advantages of this approach are that any processor can be emulated in the PTA, its ISA can be extended and special accelerators can be added too. Small loops are created directly inside the PTA and small concurrent Finite State Automats (FSM) can be This paper describes a novel Packet Triggered Architecture (PTA). This architecture takes advantage of programmable pipeline and parallel processing, which lead to MIMD (Multiple Instruction Multiple Data) architecture. The PTA is composed of two main blocks. The first block is constituted from Functional Units (FUs) and their interconnection network. The instructions in the PTA are composed of instruction packets. Every packet encapsulates a data and route across internal NoC (Network on Chip) to which enables dynamic data flow scheduling. This approach brings a new way of programming, because the programming is done by specifying FUs addresses and functions ports. Using of such a design allows create target hardware like a software application. The main advantages of this approach are that any processor can be emulated in the PTA, its ISA can be extended and special accelerators can be added too. Small loops are created directly inside the PTA and small concurrent Finite State Automats (FSM) can be (en)
Title	Introduction to the New Packet Triggered Architecture for Pipelined and Parallel Data Processing Introduction to the New Packet Triggered Architecture for Pipelined and Parallel Data Processing (en)
skos:prefLabel	Introduction to the New Packet Triggered Architecture for Pipelined and Parallel Data Processing Introduction to the New Packet Triggered Architecture for Pipelined and Parallel Data Processing (en)
skos:notation	RIV/00216305:26220/11:PU92764!RIV12-MSM-26220___
http://linked.open...avai/riv/aktivita	P S Z
http://linked.open...avai/riv/aktivity	P(GD102/08/H027), S, Z(MSM0021630513)
http://linked.open...vai/riv/dodaniDat	2012
http://linked.open...aciTvurceVysledku	Adamec, Filip Frýza, Tomáš
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta elektrotechniky a komunikačních technologií
http://linked.open...dnocenehoVysledku	205616
http://linked.open...ai/riv/idVysledku	RIV/00216305:26220/11:PU92764
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Packet Triggered Architecture, Transport Triggered Architecture, Accelerators, Network on Chip, Programmable hardware, Emulation. (en)
http://linked.open.../riv/klicoveSlovo	Accelerators Emulation. Network on Chip Packet Triggered Architecture Programmable hardware Transport Triggered Architecture
http://linked.open...ontrolniKodProRIV	[54880ACBD08F]
http://linked.open...v/mistoKonaniAkce	Brno
http://linked.open...i/riv/mistoVydani	Brno, Czech Republic
http://linked.open...i/riv/nazevZdroje	Proceedings of 21st International Conference Radioelektronika 2011
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...vavai/riv/projekt	Advanced Methods, Structures and Components of Electronic Wireless Communication
http://linked.open...UplatneniVysledku	2011
http://linked.open...iv/tvurceVysledku	Adamec, Filip Frýza, Tomáš
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2011-04-19 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Advanced Electronic Communication Systems and Technologies (ELCOM)
number of pages	4 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií. Ústav radioelektroniky
https://schema.org/isbn	978-1-61284-322-3
http://localhost/t...ganizacniJednotka	26220

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