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  • The presented work deals with design and analysis of a pipelined analog-to-digital converter (ADC). There exist error sources such as finite DC gain of opamp, capacitor mismatch, opamp bandwidth, etc., arising when the switched capacitor (SC) technique and CMOS technology are used. These error sources are explained and their influences on overall parameters of the pipelined ADC are studied. The pipelined ADC was simulated in MATLAB-Simulink and CADENCE simulation environment.
  • The presented work deals with design and analysis of a pipelined analog-to-digital converter (ADC). There exist error sources such as finite DC gain of opamp, capacitor mismatch, opamp bandwidth, etc., arising when the switched capacitor (SC) technique and CMOS technology are used. These error sources are explained and their influences on overall parameters of the pipelined ADC are studied. The pipelined ADC was simulated in MATLAB-Simulink and CADENCE simulation environment. (en)
Title
  • Pipelined ADC Design Requirements
  • Pipelined ADC Design Requirements (en)
skos:prefLabel
  • Pipelined ADC Design Requirements
  • Pipelined ADC Design Requirements (en)
skos:notation
  • RIV/00216305:26220/11:PU92080!RIV11-MSM-26220___
http://linked.open...avai/riv/aktivita
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  • S
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  • 220415
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  • RIV/00216305:26220/11:PU92080
http://linked.open...riv/jazykVysledku
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  • Pipelined ADC, MDAC, opamp (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [D41A3D1D1F44]
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  • Brno
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  • Brno
http://linked.open...i/riv/nazevZdroje
  • Proceedings of the 17th Conference STUDENT EEICT 2011
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  • Kledrowetz, Vilém
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number of pages
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  • NOVPRESS s.r.o.
https://schema.org/isbn
  • 978-80-214-4273-3
http://localhost/t...ganizacniJednotka
  • 26220
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