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  • In this work the concept of design time configurable processor is introduced. The basic architecture of designed processor core and the basic instruction set. There are described minimal core configuration (integer core) and its programming model. Processor tightly coupled peripheral like a Cache, Memory Management Unit, Protection Unit and Segment Unit are introduced. There are as well the proposed blocks for power management and power save modes. In the conclusion, the comparison between other similar designs is outlined. There is summarized actual state of work and future work is proposed as well.
  • In this work the concept of design time configurable processor is introduced. The basic architecture of designed processor core and the basic instruction set. There are described minimal core configuration (integer core) and its programming model. Processor tightly coupled peripheral like a Cache, Memory Management Unit, Protection Unit and Segment Unit are introduced. There are as well the proposed blocks for power management and power save modes. In the conclusion, the comparison between other similar designs is outlined. There is summarized actual state of work and future work is proposed as well. (en)
Title
  • Design -Time Configurable Processor Basic Structure
  • Design -Time Configurable Processor Basic Structure (en)
skos:prefLabel
  • Design -Time Configurable Processor Basic Structure
  • Design -Time Configurable Processor Basic Structure (en)
skos:notation
  • RIV/00216305:26220/10:PU86536!RIV11-GA0-26220___
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GA102/09/0776), P(GD102/08/H027), S, Z(MSM0021630513)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
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http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 253582
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26220/10:PU86536
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • Design-time configurable processor, tightly coupled peripheral, integer core, power management. (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [F6EB1C22CA01]
http://linked.open...v/mistoKonaniAkce
  • Vienna
http://linked.open...i/riv/mistoVydani
  • Vienna, Austria
http://linked.open...i/riv/nazevZdroje
  • Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems.
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
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http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Adamec, Filip
  • Frýza, Tomáš
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
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  • Vienna University of Technology, Austria
https://schema.org/isbn
  • 978-1-4244-6610-8
http://localhost/t...ganizacniJednotka
  • 26220
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